[VHDL] Personnal type as port

[Sylvain Munaut]

Hi

I know how to define a personal type to use as a signal but how to use one as a port ?


Sylvain Munaut

 

[Alan Fitch]

"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in
message news:410a7cfe$0$31463$ba620e4c@news.skynet.be...

Hi

I know how to define a personal type to use as a signal but how to
use one as a port ?

You must declare the type in a package. If you do
it all in one file, this will work...

library IEEE;
use IEEE.std_logic_1164.all;
package mytypes is
subtype ByteT is std_logic_vector(7 downto 0);
end package mytypes;

use WORK.mytypes.all;

library IEEE;
use IEEE.std_logic_1164.all;

entity e is
port (i : in mytype;
o : out std_logic_vector(15 downto 0));
end entity e;

architecture a of e is

begin

process(i)
begin
o <= i & i;
end process;
end architecture a ;

This of course is a subtype rather than a type, but
the principle is the same,

regards

Alan


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