VHDL package Verilog testbench

[rik]

Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik

 

[Ajeetha]

Hi Rik,
AFAIK this is not possible. Why do you need to do it? What does
that package contain? Type definitions? Procedures? Functions?
Components?

Also, do you have SystemVerilog aware tool? SV adds typedef etc. hence
a quick package translation might work for you.

Regards
Ajeetha, CVC
www.noveldv.com

rik wrote:

Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik

 

[rik]

Hi Ajeetha

Actually this package consists of some functions which prints strings
used for waveform labeling purpose. I dont have enough time to write it
again in verilog and so was thinking how can I include it in my
testbench.

In my testbench I will call the functions in the package which will
print my stuff.

Rik


Ajeetha wrote:

Hi Rik,
AFAIK this is not possible. Why do you need to do it? What does
that package contain? Type definitions? Procedures? Functions?
Components?

Also, do you have SystemVerilog aware tool? SV adds typedef etc. hence
a quick package translation might work for you.

Regards
Ajeetha, CVC
www.noveldv.com

rik wrote:
Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik

 

[Ajeetha]

Hi Rik,
So you want to pass a string from Verilog to a VHDL function and
print it from within VHDL - is that correct? I assume you have a MX
simulator (VHDL + Verilog) at your disposal. I don't believe you can do
this with packages, if you instead wrap this in an entity/arch then it
is easy to do. Of-course the entity can use that VHDL package, so all
you will need is an entity wrapper.

Show a simple piece of code that demonstrates your requirement, I can
try and show you how to do this via entity-arch pair.

Regards
Ajeetha, CVC
www.noveldv.com

rik wrote:

Hi Ajeetha

Actually this package consists of some functions which prints strings
used for waveform labeling purpose. I dont have enough time to write it
again in verilog and so was thinking how can I include it in my
testbench.

In my testbench I will call the functions in the package which will
print my stuff.

Rik
Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik

 

Verilog and VHDL languages cannot be bound at compile time. By
definition, one languages do not accept the other. You cannot call a
VHDL procedure directly from a Verilog module. You can mix both only
during elaboration time.

You must therefore call the packages from a VHDL entity/architecture. A
VHDL entity/architecture can be instantiated in a Verilog environment
using default binding rules, or FOREIGN interface supported by Verilog
tool.

This will of course cost you time to develop VHDL interfaces.

You have following choices:
1. Choose a VHDL testbench (if possible)
2. Write VHDL entity/architecture for each item in VHDL package
3. Write Verilog code for each item in VHDL package

Utku

Ajeetha wrote:

Hi Rik,
So you want to pass a string from Verilog to a VHDL function and
print it from within VHDL - is that correct? I assume you have a MX
simulator (VHDL + Verilog) at your disposal. I don't believe you can do
this with packages, if you instead wrap this in an entity/arch then it
is easy to do. Of-course the entity can use that VHDL package, so all
you will need is an entity wrapper.

Show a simple piece of code that demonstrates your requirement, I can
try and show you how to do this via entity-arch pair.

Regards
Ajeetha, CVC
www.noveldv.com

rik wrote:
Hi Ajeetha

Actually this package consists of some functions which prints strings
used for waveform labeling purpose. I dont have enough time to write it
again in verilog and so was thinking how can I include it in my
testbench.

In my testbench I will call the functions in the package which will
print my stuff.

Rik
Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik

 

Are you using Mnemonic Map feature of Cadence NC-Sim? It does the stuff
you want.

Why don't you take Tcl? You can construct Tcl script for that stuff.
In that case you can get rid of VHDL/Verilog melting pot and you will
have language-independent simulation environment with no cost of
compilation/elaboration time.

Utku

rik wrote:

Hi Ajeetha

Actually this package consists of some functions which prints strings
used for waveform labeling purpose. I dont have enough time to write it
again in verilog and so was thinking how can I include it in my
testbench.

In my testbench I will call the functions in the package which will
print my stuff.

Rik


Ajeetha wrote:
Hi Rik,
AFAIK this is not possible. Why do you need to do it? What does
that package contain? Type definitions? Procedures? Functions?
Components?

Also, do you have SystemVerilog aware tool? SV adds typedef etc. hence
a quick package translation might work for you.

Regards
Ajeetha, CVC
www.noveldv.com

rik wrote:
Hi guys

I have a package in VHDL which I need to use in a verilog test-bench.
How do I include the package?

I used

`include print_util.vhd in my test.v(testbench)

and its complaining about the vhdl code, may be coz it thinks it to be
verilog.
So freinds how ill I include the package?


Rik