VHDL newbie

[Trent R.]

Hello,

I started now with VHDL....so maybe it´s a stupid Question....
but is there an easy way to increment a bitvector?
For example something like this:

SIGNAL nano_bin : std_ulogic_vector(31 downto 0);
IF....THEN
nano_bin <= nano_bin +1 ;
END IF;

THX Trent

 

[Simon Peacock]

you can add X"00000001" to the result.. or if you include the right file....
'use ieee.std_logic_signed.all' (I think) then the conversion from 1 to
X"00000001" is done automatically.

but you might want to try

library ieee;
use ieee.std_logic_signed.all;

....

if (...) then
if (nano_bit /= X"FFFFFFFF") then -- I think you can use (others =>
'1') instead of X"FFFFFFFF" here
nano_bit <= nano_bit + 1;
else
nano_bit <= 0;
end if;
end if;


Simulators will tend to barf as an overflow will occur when the counter
reaches max and increments so good practice is to limit the range of a
counter. This also makes the counter have a readable limit.

Simon


"Trent R." <rnenna@gmx.de> wrote in message
news:buu99a$acv$1@ngspool-d02.news.aol.com...

Hello,

I started now with VHDL....so maybe it´s a stupid Question....
but is there an easy way to increment a bitvector?
For example something like this:

SIGNAL nano_bin : std_ulogic_vector(31 downto 0);
IF....THEN
nano_bin <= nano_bin +1 ;
END IF;

THX Trent

 

[Jim Lewis]

Use package numeric_std from IEEE and the type unsigned.

library ieee ;
use ieee.numeric_std.all ;

.. . .

SIGNAL nano_bin : unsigned(31 downto 0);
IF....THEN
nano_bin <= nano_bin +1 ;
END IF;

Currently there is no package that directly supports
the type std_ulogic_vector. There is a package that
supports std_logic_vector (called std_logic_unsigned).
Some like it, some don't. The argument is that whenever
possible, use the type unsigned as it contains
documentation in the type. My thought is that for
somethings (such as testbenches) it is unpractical to not
use std_logic_unsigned (at least until we have something
better from IEEE).

The use of std_logic_unsigned is clear as long as you
never use the package std_logic_signed.

Regards,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Trent R. wrote:

Hello,

I started now with VHDL....so maybe it´s a stupid Question....
but is there an easy way to increment a bitvector?
For example something like this:

SIGNAL nano_bin : std_ulogic_vector(31 downto 0);
IF....THEN
nano_bin <= nano_bin +1 ;
END IF;

THX Trent