VHDL newbie

[Joseph A. Zammit]

Hi,

I have just begun learning VHDL. I am a telecommunications engineer
and an electronics hobbyist. I have some quieries:

1. I need some small projects to start with. I have tried counters,
multiplexers ect already but i need some harder examples involving
more sequential logic.

2. I am using Xilinx Coolrunner II CPLD's. Where can i find
information relating to what subset is implemented by the compiler for
the CPLD? For example how is the 'after 10ns' implemented in the CPLD?
or it is ignored by the system?

3. Any other useful tips and pointers that misght be helpful.

Thanks for your help beforehand

Joseph A. Zammit
Malta

 

[Nicolas Matringe]

Joseph A. Zammit a écrit:

Hi,
[...]
2. I am using Xilinx Coolrunner II CPLD's. Where can i find
information relating to what subset is implemented by the compiler for
the CPLD? For example how is the 'after 10ns' implemented in the CPLD?
or it is ignored by the system?

Such statements are *always* ignored by synthesis tools. This is part of
the non-synthesizable subset of VHDL.

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Tim Hubberstey]

"Joseph A. Zammit" wrote:

Hi,

I have just begun learning VHDL. I am a telecommunications engineer
and an electronics hobbyist. I have some quieries:

1. I need some small projects to start with. I have tried counters,
multiplexers ect already but i need some harder examples involving
more sequential logic.

UARTs, traffic light controllers (always a favorite with the teaching
types), LED signs...

2. I am using Xilinx Coolrunner II CPLD's. Where can i find
information relating to what subset is implemented by the compiler for
the CPLD? For example how is the 'after 10ns' implemented in the CPLD?
or it is ignored by the system?

*ANY* VHDL constructs that specify time are ignored by synthesizers.
These are purely simulation features.

Go to the Xilinx web pages for many thousands (I'm not joking!) of pages
of documentation on the tools, including what you're looking for. The
Synthesis and Verification Design Guide should be your first stop.

3. Any other useful tips and pointers that misght be helpful.
^

Use a spell checker ;-) ----------------------+
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[valentin tihomirov]

3. Any other useful tips and pointers that misght be helpful.
^
Use a spell checker ;-) ----------------------+

Spell checker will not find any english grammar errors since *pointer* is a
valid word.

 

[Jonathan Bromley]

WARNING: Any humorous content in this message will be utterly
lost unless viewed in a fixed-space font such as Courier.

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote
in message news:c0vmip$1ccg8f$1@ID-212430.news.uni-berlin.de...

3. Any other useful tips and pointers that misght be helpful.
^
Use a spell checker ;-) ----------------------+

Spell checker will not find any english grammar errors since *pointer* is
a
valid word.

Those who live by proportionally spaced fonts will die thereby...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[valentin tihomirov]

Those who live by proportionally spaced fonts will die thereby...

We all die :-( earlier or later.
BTW, most of us use default fonts. MS ergonomics department recommends them.

 

[Tim Hubberstey]

valentin tihomirov wrote:

Those who live by proportionally spaced fonts will die thereby...

We all die :-( earlier or later.
BTW, most of us use default fonts. MS ergonomics department recommends them.

Well then your MS ergonomics department are, to be blunt, idiots. "Most"
people reading technical newsgroups DO NOT use proportional fonts for
exactly the reason you've just discovered. It is very often necessary to
show a position in reference to other lines in a post and these are
impossible with proportional fonts since each font has its own character
spacing. You also can't draw pictures with a proportional font. Try
reading a group like sci.electronics.design with a proportional font and
see how much you'll be able to understand.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Jonathan Bromley]

"Tim Hubberstey" <bogus@bogusname.com> wrote in message
news:6ZNYb.30198$Hy3.18358@edtnps89...

valentin tihomirov wrote:
[..]
BTW, most of us use default fonts. MS ergonomics department recommends
them.

Well then your MS ergonomics department are, to be blunt, idiots.

I *suspect* that Valentin was being sarcastic...

Try reading a group like sci.electronics.design with
a proportional font and
see how much you'll be able to understand.

hmmm... I gave up on s.e.d a little while ago, as the aggression
was getting a bit much for me. However, mentioning s.e.d gives
me another excuse to plug Andy Weber's delightful program
AACircuit for drawing ASCII-art:

http://www.tech-chat.de/AAcircuit.html

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.