VHDL model procesora RISC(DLX)

[Paweł Miernik]

Witam.
Potrzebuje materiały dotyczące architektury RISC(DLX)
oraz implementacji tej architektury w języku VHDL.
Pozdrawiam
PM

 

[Ziggy]

Eric DELAGE wrote:

I guess that you'll have more success if you write in English.
Are you looking for a VHDL implementation of DLX?

Eric

While we have no idea what he asked so i may not be OT.. i was wondering

if anyone around here has done much with DLX.

Im planning on getting back in to digital logic, and starting with
FPGAs, so was looking for something i can get my head around until i get
back into the swing of things, and DLX seemed to fit the bill. Just got
the 'big book' in the mail yesterday.

Perhaps couple it with some other prebuilt open cores like VGA,
ethernet, usb, etc..

The fact it can run a real OS is also a plus.. the last time i did this
( late 70's ) had to write my own OS and language too.. back then the
extra work was fun.. today.. i donno ).

 

[Eric DELAGE]

Hi

Does someone know where I could find the DLX specification? which s/w
dev tools exists? which rtos were ported to a DLX processor?

Eric

While we have no idea what he asked so i may not be OT.. i was wondering
if anyone around here has done much with DLX.

 

[Ziggy]

Eric DELAGE wrote:

Hi

Does someone know where I could find the DLX specification? which s/w
dev tools exists? which rtos were ported to a DLX processor?

Eric

While we have no idea what he asked so i may not be OT.. i was
wondering if anyone around here has done much with DLX.

Start here -> http://www.ics.forth.gr/carv/aspida/

 

[Eric DELAGE]

I guess that you'll have more success if you write in English.
Are you looking for a VHDL implementation of DLX?

Eric