VHDL model of Xilinx's Rocket I/O MGT

[Tim]

Good evening, everybody,

Now - before I get cracking on creating a VHDL model of Xilinx's Rocket I/O MGT
- has anyone else done this already? And would they be willing to share it out
of the goodness of their heart?

Cheers,
Tim.

 

[General Schvantzkoph]

On Sat, 24 Jul 2004 21:35:56 +0000, Tim wrote:

Good evening, everybody,

Now - before I get cracking on creating a VHDL model of Xilinx's Rocket I/O MGT
- has anyone else done this already? And would they be willing to share it out
of the goodness of their heart?

Cheers,
Tim.

There are SWIFT models provided by Xilinx.

 

[Tim]

Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator
- bit of a bugger if you've only got Modelsim XE.

 

[General Schvantzkoph]

On Sun, 25 Jul 2004 08:10:33 +0000, Tim wrote:

Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator
- bit of a bugger if you've only got Modelsim XE.

The performance is also awful. My testbench takes a 10 to 1 performance
hit when using the RocketIO SWIFT models (I use them in both NCverilog and
ModelSim, it cripples both of them). Would Peter or Austin please explain
why Xilinx decided to use SWIFT models instead of a plain Verilog model.
The secrets in a SerDes are at the transistor level not at the logic
level. A nice fast bus functional Verilog model would have been prefered
by all.

 

[alessio quagliariello]

Hello! I have a problem with the swift interface and ModelSim.. when I try to load my project the follow error are returned :# Loading D:/CAE_Tools/Modeltech_5.8/win32pe/libsm.dll <br>
# ** Error: Failed to find LMC SmartModel libswift entry in project file. <br>
# ** Fatal: Foreign module requested halt. <br><br>I would like to know the cause of this error.. Best regards, alessio

 

[Austin Lesea]

GS,

The ip of the 3.125 Gbs transceivers in the Virtex II Pro was developed
by Connexant, and does not belong to us. We do not have the luxury of
disclosing the verilog, even if we wanted to.

Now, for the other Rocket I/O (tm) developed by us, we do have that
option. I will let the folks in charge know.

Thanks,

Austin

General Schvantzkoph wrote:

On Sun, 25 Jul 2004 08:10:33 +0000, Tim wrote:


Unfortunately, sim/n of SWIFT models requires a SWIFT-model supporting simulator
- bit of a bugger if you've only got Modelsim XE.


The performance is also awful. My testbench takes a 10 to 1 performance
hit when using the RocketIO SWIFT models (I use them in both NCverilog and
ModelSim, it cripples both of them). Would Peter or Austin please explain
why Xilinx decided to use SWIFT models instead of a plain Verilog model.
The secrets in a SerDes are at the transistor level not at the logic
level. A nice fast bus functional Verilog model would have been prefered
by all.