VHDL language of choice?

[Herb T]

Folks,
I was talking to some electronics buffs on a chat channel, and they
were telling me that only Universities and DOD uses VHDL. I thought it
was hogwash, but wanted to find out if many commercial companies are
using the language earnestly. The resident HDL expert was saying
verilog is the language of choice these days. Is that true? I
personally prefer VHDL because the I already have too many reference
materials on how to use it.
Thanks,
-HT

 

[Neo]

verilog is widely prevalent in asic design world and is the language of
choice. But in FPGA design community both are widely used.

 

[Jim Lewis]

Herb,
The statistics I heard was that in 2001 VHDL had
60% of the FPGA market. Verilog had 15% of the
FPGA market and the remaining 25% went to other
entry methods. Hence the early FPGA tool development
and FPGA model development favored VHDL.

With the a large portion of the market shifting from
ASIC to FPGA I am sure the market share has changed, but
that does not change the pre-existing intellectual
property for FPGAs being developed in VHDL.

The historic opposite happened with Verilog in the
ASIC market. Verilog was first to have a gate level
netlist, and hence, became a significant solution for
the ASIC market.

All marketing statistics I have seen where the Verilog
crowd claims to have market share are based on EDA tool
sales, where the ASIC tools cost >>> the FPGA tools, and
hence, showed that more $$$ were spent on Verilog tools.
This is a significant measure for EDA tool vendors as it
indicates where there is money to be made. It was never
a measure of users, although some would like to convince
you it is. Because of this, many emphatically believe that
Verilog has a significant lead in user adoption. It is the
difference of looking at numbers rather than looking at data.

There is an on-going revision of VHDL in progress. It is
adding a number of significant features (such as uncostrained
arrays of arrays - very useful in parameterized models),
generics on packages, packages for fixed and floating
point, integration of PSL, and language simplification
(case and if statements). In the area of math, VHDL will
have an advantage over Verilog/System Verilog as they don't
have their own solution for these fixed and floating point.
For more details see the papers page at:
http://www.synthworks.com/papers

In the next revision (immediately following this one) we will
be adding enhanced verification features, similar to what
System Verilog has done (such as constrained random). We will
also be using the new features of the language (specifically
generics on packages) to write packages that implement advanced
verification data structures (such as queues, FIFOS, and
memories).

Best Regards,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Folks,
I was talking to some electronics buffs on a chat channel, and they
were telling me that only Universities and DOD uses VHDL. I thought it
was hogwash, but wanted to find out if many commercial companies are
using the language earnestly. The resident HDL expert was saying
verilog is the language of choice these days. Is that true? I
personally prefer VHDL because the I already have too many reference
materials on how to use it.
Thanks,
-HT

 

[Paul]

* finally: VHDL code it better human-readable - IMHO ;-)

I used to think that vhdl would be more readable than verilog, but I've
seen too much vhdl code that looks like this:

x := std_logic_vector(to_unsigned((to_integer(unsigned(z1)) +
to_integer(unsigned(z2))), 9));
y := std_logic_vector(to_unsigned((to_integer(unsigned(x(7
DOWNTO 0))) + to_integer(unsigned(x(8
DOWNTO 8)))), 8));

which I *think* is meant to do the same thing as this nice verilog
code:

x = z1 + z2;
y = x[7:0] + x[8];

(Now try to imagine the above vhdl code with really long identifiers
instead of
the short identifiers that I used.)

Some vhdl proponents believe that readability is synonymous with
verbosity.

Paul