[vhdl] how to wire two signals together? alias not adequate

[Khashishi]

If I have a signals a and b, how can I make another signal c === a &
b.
I want to be able to assign c, and automatically update a and b.
In addition, I want to be able to assign a, and update c. I want them
to physically refer to the same signal. This is for convenience and
maintainability reasons.

I can't use assigment, because vhdl assignment operators are
directional, which makes no real physical sense to me.
So if I do
c <= a & b;
I can't assign c to update a & b, because then it would be multiple
drivers.

Verilog has a wire command which does what I want. I'm constrained to
vhdl.
Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;
(You'll tell me, it's not allowed in VHDL. Well, I can't see any
reason why it shouldn't be allowed.)
I could do:
alias a is c(0);
alias b is c(1);
; however, this method won't allow me to set a as a port out variable
which I want to define in an upper level.

I think it might be possible to instantiate some component and route
a, b, c through the port mapping somehow, but this just seems tortuous
and contra my goal of convenience and maintainability.

Is VHDL inadequate to provide a solution to this? Or am I just missing
something?

 

[Jeroen]

"Khashishi" <spam@mailinator.com> wrote in message
news:f90f4bdc.0409211114.3fbf742b@posting.google.com...

If I have a signals a and b, how can I make another signal c === a &
b.
I want to be able to assign c, and automatically update a and b.
In addition, I want to be able to assign a, and update c. I want them
to physically refer to the same signal. This is for convenience and
maintainability reasons.

I can't use assigment, because vhdl assignment operators are
directional, which makes no real physical sense to me.
So if I do
c <= a & b;
I can't assign c to update a & b, because then it would be multiple
drivers.

Verilog has a wire command which does what I want. I'm constrained to
vhdl.
Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;
(You'll tell me, it's not allowed in VHDL. Well, I can't see any
reason why it shouldn't be allowed.)
I could do:
alias a is c(0);
alias b is c(1);
; however, this method won't allow me to set a as a port out variable
which I want to define in an upper level.

I think it might be possible to instantiate some component and route
a, b, c through the port mapping somehow, but this just seems tortuous
and contra my goal of convenience and maintainability.

Is VHDL inadequate to provide a solution to this? Or am I just missing
something?

After reading this a few times I see what you want to do, but I fail to see
the why. In C you could use a union to do what you want, or do some wizardry
with pointers. But I think it cannot be classified as a good coding practise
to have 3 different names that are the same signal.

Jeroen

 

[rickman]

Khashishi wrote:

If I have a signals a and b, how can I make another signal c === a &
b.
I want to be able to assign c, and automatically update a and b.
In addition, I want to be able to assign a, and update c. I want them
to physically refer to the same signal. This is for convenience and
maintainability reasons.

Personally I don't see how this would improve maintainability. In fact,
it can reduce it since it sounds like you want to be able to assign this
"wire" in separate modules which would be very hard to debug.

I can't use assigment, because vhdl assignment operators are
directional, which makes no real physical sense to me.
So if I do
c <= a & b;
I can't assign c to update a & b, because then it would be multiple
drivers.

Verilog has a wire command which does what I want. I'm constrained to
vhdl.
Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;
(You'll tell me, it's not allowed in VHDL. Well, I can't see any
reason why it shouldn't be allowed.)
I could do:
alias a is c(0);
alias b is c(1);
; however, this method won't allow me to set a as a port out variable
which I want to define in an upper level.

If a is an out port, then why can't you use an assignment? Or assign a
to z and use z in the output port.

I think it might be possible to instantiate some component and route
a, b, c through the port mapping somehow, but this just seems tortuous
and contra my goal of convenience and maintainability.

Is VHDL inadequate to provide a solution to this? Or am I just missing
something?

I think I am missing the reason that you want to do this. Where are the
different assignments to this one wire? Normally assigning values to a
signal can only be done in a single process or concurrent assignment
unless it is a tristate bus. Is that what you are doing? If so, you
might want to use inout port for a.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Weng Tianxiang]

Aliases don't have the full flexibility of signals in vhdl. I can't
seem to build an alias like this:
alias c(1) is b;
alias c(0) is a;

You can do it, but you did it wrongly.

The correct statements should look like this:

signal C : std_logic_vector(5 downto 0);
alias a : std_logic is C(0);
alias b : std_logic is C(1);

a, b are only a different name for C(0)/C(1), absolutely like in C.

Weng