VHDL horror in Xcell 76

[RCIngham]

There is an utterly horrible VHDL howler on page of 45 of the latest Xcel
Journal. Two example codes for a register with reset are given:

signal Q: std_logic:=‘1’;
....
async: process (CLK,RST)
begin
if (RST= ‘1’) then
Q <= ‘0’;
elsif (rising_edge CLK) then
Q <= D;
end if;
end

This would be OK if the clock edge function call had bee
'rising_edge(CLK)' instead, and there was a semi-colon after the las
'end'.


signal Q: std_logic:=‘1’;
....
async: process (CLK)
begin
if (RST= ‘1’) then
Q <= ‘0’;
elsif (rising_edge CLK) then
Q <= D;
end if;
end

This has the same errors as the first, but (despite the unchanged proces
name) is meant to infer a synchronously reset register. BUT ALAS AND ALACK
As written - at least in simulation - the reset will be applied on eithe
edge of CLK. What XST would make of it can only guess. It should be:

signal Q: std_logic:='1';
....
sync: process (CLK)
begin
if rising_edge(CLK) then
if (RST= '1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process sync;

Such slip-shop work rather reduces one's confidence in the rest of th
contents.


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[RCIngham]

I should have added that this is also at:
http://forums.xilinx.com/t5/General-Technical-Discussion/VHDL-horror-in-Xcell-76/td-p/167622


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[Kolja Sulimma]

On Jul 27, 11:53 am, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

It should be:
...
sync: process (CLK)
begin
  if rising_edge(CLK) then
...
end process sync;

actually it should be
sync: process (all)
begin
....
end process;

At least there was VHDL-2008 support announced for ISE11.1...

Kolja

 

[Gabor]

On Jul 27, 5:59 am, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

I should have added that this is also at:http://forums.xilinx.com/t5/General-Technical-Discussion/VHDL-horror-...

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Cute article. If only Xilinx would take some of their own
advice on resets...

Tip #4 - Use active high control signals. (For some reason
MIG defaults to active low reset).

Where's the tip on running your VHDL through syntax check
before publishing it in a journal?

Cheers,
Gabor

 

[valtih1978]

Listening for all synchronizes your RST with CLK. Right?

 

[RCIngham]

Listening for all synchronizes your RST with CLK. Right?

"process (all) is" not, AFAIK, supported yet by XST.

Anyway, if you want to know how to synchronize resets, read this paper:
http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf



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[valtih1978]

Ok. You used a tricky way to say that Kolja actually meant

_A_sync: process(all)

 

[E Srikanth]

On Aug 3, 7:42 am, valtih1978 <d...@not.email.me> wrote:

Ok. You used a tricky way to say that Kolja actually meant

        _A_sync: process(all)

Hi All,

I am E Srikanth , and the author of the XCell Article " how do I reset
my FPGA.

I accept that there were few errors in the article after that has been
published. But the the errors have been fixed within few days after
the day of publishing.
Please download the pdf file again for all the corrections.

http://issuu.com/xcelljournal/docs/xcell_journal_issue_76/44?viewMode=magazine&mode=embed


Regards,
E Srikanth