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Bruno Carvalho

Guest
Hello,

I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.
I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.
In this simulation the behavior of tx_controller is correct.
But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.

Bellow is my code

--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------

ENTITY tx_controller IS
GENERIC(WR_USED_MIN: integer := 376;
NULL_PACKET: integer := 255);
PORT (clk, rst: IN STD_LOGIC;
data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER
fifo_is_empty: IN STD_LOGIC;
wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER
fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING
data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE
);
END tx_controller;

ARCHITECTURE behav OF tx_controller IS
CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));
BEGIN

MAIN: PROCESS(rst, clk, data_in, wr_used)
BEGIN
IF (rst = '1') THEN
fifo_rd_enable <= '0';
data_out <= (others => '0');
ELSIF (rising_edge(clk)) THEN
IF (wr_used < fifo_min) THEN
data_out <= (OTHERS => '1');
fifo_rd_enable <= '0';
ELSE
fifo_rd_enable <= '1';
data_out <= data_in;
END IF;
END IF;
END PROCESS;
END behav;


Somebody can identify some problem analysing my vhdl code ?

Thanks for any help.
 
Am Donnerstag, 26. Juli 2012 04:02:42 UTC+2 schrieb Bruno Carvalho:
Hello,

I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.
I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.
In this simulation the behavior of tx_controller is correct.
But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.

Bellow is my code

--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------

ENTITY tx_controller IS
GENERIC(WR_USED_MIN: integer := 376;
NULL_PACKET: integer := 255);
PORT (clk, rst: IN STD_LOGIC;
data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER
fifo_is_empty: IN STD_LOGIC;
wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER
fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING
data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE
);
END tx_controller;

ARCHITECTURE behav OF tx_controller IS
CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));
BEGIN

MAIN: PROCESS(rst, clk, data_in, wr_used)
BEGIN
IF (rst = '1') THEN
fifo_rd_enable <= '0';
data_out <= (others => '0');
ELSIF (rising_edge(clk)) THEN
IF (wr_used < fifo_min) THEN
data_out <= (OTHERS => '1');
fifo_rd_enable <= '0';
ELSE
fifo_rd_enable <= '1';
data_out <= data_in;
END IF;
END IF;
END PROCESS;
END behav;


Somebody can identify some problem analysing my vhdl code ?

Thanks for any help.
Click to expand...
Hi,
how have you simulated your code?
With a separate testbench, or together with the rest of the design, especially that FIFO-IP simulation model?

Without the FIFO-IP model your testbench might behave different and so your code may have some +/-1 Error in the comparator numbers due to some signal latency.

Have a nice simulation
Eilert
 
Hello,

Thanks for your reply.

Well, when i simulate the component alone it works correctly.

But when i run a simulation with the component integrated to my system by port maps, the behavior is wrong.

Could i consider your commentary about delay once i'm doing a functional simulation ? Sorry if i'm doing a silly question.

Thank you so much.

Best Regards.

Bruno

On Wednesday, July 25, 2012 10:02:42 PM UTC-4, Bruno Carvalho wrote:
Hello,



I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.

I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.

In this simulation the behavior of tx_controller is correct.

But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.



Bellow is my code



--------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

--------------------------------------------------------------



ENTITY tx_controller IS

GENERIC(WR_USED_MIN: integer := 376;

NULL_PACKET: integer := 255);

PORT (clk, rst: IN STD_LOGIC;

data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER

fifo_is_empty: IN STD_LOGIC;

wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER

fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING

data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE

);

END tx_controller;



ARCHITECTURE behav OF tx_controller IS

CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));

BEGIN



MAIN: PROCESS(rst, clk, data_in, wr_used)

BEGIN

IF (rst = '1') THEN

fifo_rd_enable <= '0';

data_out <= (others => '0');

ELSIF (rising_edge(clk)) THEN

IF (wr_used < fifo_min) THEN

data_out <= (OTHERS => '1');

fifo_rd_enable <= '0';

ELSE

fifo_rd_enable <= '1';

data_out <= data_in;

END IF;

END IF;

END PROCESS;

END behav;





Somebody can identify some problem analysing my vhdl code ?



Thanks for any help.
Click to expand...
 
Am Dienstag, 31. Juli 2012 03:45:36 UTC+2 schrieb Bruno Carvalho:
Hello,



Thanks for your reply.



Well, when i simulate the component alone it works correctly.



But when i run a simulation with the component integrated to my system by port maps, the behavior is wrong.



Could i consider your commentary about delay once i'm doing a functional simulation ? Sorry if i'm doing a silly question.



Thank you so much.



Best Regards.



Bruno



On Wednesday, July 25, 2012 10:02:42 PM UTC-4, Bruno Carvalho wrote:

Hello,







I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.



I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.



In this simulation the behavior of tx_controller is correct.



But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.







Bellow is my code







--------------------------------------------------------------



library IEEE;



use IEEE.std_logic_1164.all;



use IEEE.numeric_std.all;



--------------------------------------------------------------







ENTITY tx_controller IS



GENERIC(WR_USED_MIN: integer := 376;



NULL_PACKET: integer := 255);



PORT (clk, rst: IN STD_LOGIC;



data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER



fifo_is_empty: IN STD_LOGIC;



wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER



fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING



data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE



);



END tx_controller;







ARCHITECTURE behav OF tx_controller IS



CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));



BEGIN







MAIN: PROCESS(rst, clk, data_in, wr_used)



BEGIN



IF (rst = '1') THEN



fifo_rd_enable <= '0';



data_out <= (others => '0');



ELSIF (rising_edge(clk)) THEN



IF (wr_used < fifo_min) THEN



data_out <= (OTHERS => '1');



fifo_rd_enable <= '0';



ELSE



fifo_rd_enable <= '1';



data_out <= data_in;



END IF;



END IF;



END PROCESS;



END behav;











Somebody can identify some problem analysing my vhdl code ?







Thanks for any help.
Click to expand...
Hi Bruno,
When simulating a system consisting of synchronous designs the outputs are mostly registered.

So the behavior is well defined.

In many testbenches designers use WAIT FOR statements to assign their stimuli.
And Most often these statements are causing signals to change at the active clock edge. This is a big problem.

While in the waveform this looks like a registered output, the attached FFs can show undetermined behavior. Wether the old state of the signal is taken by the FF or the new one can't be said. That depends on the sequence of signal changes in the delta cycles for that time.

So please check your testbench if you are using WAIT FOR statements.
(AFTER statements can cause similar problems)

You can overcome this by using e.g.
WAIT UNTIL rising_edge(clk);
after each WAIT FOR. (shorten the time in the WAIT FOR for some ns)


The tricky thing is, that your waveform might look OK, but it isnt.
And you can't see it because the malbehavior is hidden in the delta cycles.
But as soon as you connect your module with other modules that have true registered outputs you observe strange behavior , as you did. Especially when you are using comparators, they are probably all misaligned.

Have a nice simulation
Eilert
 
goouse99@googlemail.com wrote:
Am Dienstag, 31. Juli 2012 03:45:36 UTC+2 schrieb Bruno Carvalho:
Hello,



Thanks for your reply.



Well, when i simulate the component alone it works correctly.



But when i run a simulation with the component integrated to my system by port maps, the behavior is wrong.



Could i consider your commentary about delay once i'm doing a functional simulation ? Sorry if i'm doing a silly question.



Thank you so much.



Best Regards.



Bruno



On Wednesday, July 25, 2012 10:02:42 PM UTC-4, Bruno Carvalho wrote:

Hello,
I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.
I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.
In this simulation the behavior of tx_controller is correct.
But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.
Bellow is my code
--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------
ENTITY tx_controller IS
GENERIC(WR_USED_MIN: integer := 376;
NULL_PACKET: integer := 255);
PORT (clk, rst: IN STD_LOGIC;
data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER
fifo_is_empty: IN STD_LOGIC;
wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER
fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING
data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE
);
END tx_controller;
ARCHITECTURE behav OF tx_controller IS
CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));
BEGIN
MAIN: PROCESS(rst, clk, data_in, wr_used)
BEGIN
IF (rst = '1') THEN
fifo_rd_enable <= '0';
data_out <= (others => '0');
ELSIF (rising_edge(clk)) THEN
IF (wr_used < fifo_min) THEN
data_out <= (OTHERS => '1');
fifo_rd_enable <= '0';
ELSE
fifo_rd_enable <= '1';
data_out <= data_in;
END IF;
END IF;
END PROCESS;
END behav;
Somebody can identify some problem analysing my vhdl code ?
Thanks for any help.

Hi Bruno,
When simulating a system consisting of synchronous designs the outputs are mostly registered.

So the behavior is well defined.

In many testbenches designers use WAIT FOR statements to assign their stimuli.
And Most often these statements are causing signals to change at the active clock edge. This is a big problem.

While in the waveform this looks like a registered output, the attached FFs can show undetermined behavior. Wether the old state of the signal is taken by the FF or the new one can't be said. That depends on the sequence of signal changes in the delta cycles for that time.

So please check your testbench if you are using WAIT FOR statements.
(AFTER statements can cause similar problems)

You can overcome this by using e.g.
WAIT UNTIL rising_edge(clk);
after each WAIT FOR. (shorten the time in the WAIT FOR for some ns)


The tricky thing is, that your waveform might look OK, but it isnt.
And you can't see it because the malbehavior is hidden in the delta cycles.
But as soon as you connect your module with other modules that have true registered outputs you observe strange behavior , as you did. Especially when you are using comparators, they are probably all misaligned.

Have a nice simulation
Eilert
Click to expand...
Also your process MAIN has extra items in the sensitivity list.
I don't think this will affect simulation, but it's best to clean
it up to make sure. A clocked process should only have the clock
and any asynchronous set/reset inputs in the sensitivity list.
Synthesis generally ignores the sensitivity list, so keeping the
list correct prevents unintentional differences between simulation
and synthesis.

MAIN: PROCESS(rst, clk, data_in, wr_used)

should be:

MAIN: PROCESS(rst, clk)

-- Gabor
 
בתאריך יום חמישי, 26 ביולי 2012 09:02:44 UTC+3, מאת goou...@googlemail.com:
Am Donnerstag, 26. Juli 2012 04:02:42 UTC+2 schrieb Bruno Carvalho:

Hello,



I'm having difficulties to understand a modelsim simulation of a vhdl component written by me.

I have a vhdl component which name is tx_controller. This component has a simple logic. It reads the number of words stored in a buffer (dc_fifo altera ip core). If the number of words stored in buffer < 376, so i send to the output data_out the value 0xFF. When the words store in buffer >= 376, i send to the data_out the value of input data_in which is values came from buffer.

In this simulation the behavior of tx_controller is correct.

But when i use the same module integrated in my system through port maps the component has a strange behavior. E.g.: When the data_in has the value 0x40, data_out should receive the value 0x40, but it keeps with the last value (0x00) and the value is changed to 0x40 only in the next rising edge in clock signal.



Bellow is my code



--------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

--------------------------------------------------------------



ENTITY tx_controller IS

GENERIC(WR_USED_MIN: integer := 376;

NULL_PACKET: integer := 255);

PORT (clk, rst: IN STD_LOGIC;

data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --DATA FROM BUFFER

fifo_is_empty: IN STD_LOGIC;

wr_used: IN STD_LOGIC_VECTOR(8 DOWNTO 0); --N WORDS IN BUFFER

fifo_rd_enable: OUT STD_LOGIC; --ENABLE FIFO READING

data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --DATA TO INTERFACE

);

END tx_controller;



ARCHITECTURE behav OF tx_controller IS

CONSTANT fifo_min : STD_LOGIC_VECTOR(8 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(WR_USED_MIN, 9));

BEGIN



MAIN: PROCESS(rst, clk, data_in, wr_used)

BEGIN

IF (rst = '1') THEN

fifo_rd_enable <= '0';

data_out <= (others => '0');

ELSIF (rising_edge(clk)) THEN

IF (wr_used < fifo_min) THEN

data_out <= (OTHERS => '1');

fifo_rd_enable <= '0';

ELSE

fifo_rd_enable <= '1';

data_out <= data_in;

END IF;

END IF;

END PROCESS;

END behav;





Somebody can identify some problem analysing my vhdl code ?



Thanks for any help.



Hi,

how have you simulated your code?

With a separate testbench, or together with the rest of the design, especially that FIFO-IP simulation model?



Without the FIFO-IP model your testbench might behave different and so your code may have some +/-1 Error in the comparator numbers due to some signal latency.



Have a nice simulation

Eilert
Click to expand...
You may want to start with small VHDL examples. Make them work and then continue. For instance see what I did at:
http://bknpk.no-ip.biz/my_web/SDIO/vhdl_wait_process_select.html
 
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