VHDL has no `define like Verilog?

  • Thread starter I_likes_Verilog
  • Start date
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I_likes_Verilog

Guest
I've just started learning VHDL, and there is some convenience
feature I need ...

In verilog, I'd often use the (`ifdef) preprocessor to enclose
debugging statements.

`ifdef DBG_MY_MODULE
intial begin
$display("recognized DBG_MY_MODULE!" );
// go spam the console with extra debug messages!
//
//

`endif

In VHDL, I haven't found a way to do this...

The best I can come up with is

boolean flag_dbg_my_module := true;
begin
if ( flag_dbg_my_module ) then
report "recognized flag_dbg_my_module!";

-- go spam the console with extra debug messages!
--
--
end if; -- flag_dbg_my_module
end process;

Obviously, I can put flag_dbg_my_module in a 'package'.
But is there a more convenient/clever way to do this?
I just want some quick and dirty way to 'activate' a
block of statements (for extra debug messages.) In
Verilog, the preprocessor was great, since I could directly
activate the macro-define (`define) from the command-line

( example, 'ncverilog my_module.v +define+DBG_MY_MODULE=1;')
 
I_likes_Verilog a écrit :

I've just started learning VHDL, and there is some convenience
feature I need ...

In verilog, I'd often use the (`ifdef) preprocessor to enclose
debugging statements.
[...]
Obviously, I can put flag_dbg_my_module in a 'package'.
But is there a more convenient/clever way to do this?
I just want some quick and dirty way to 'activate' a
block of statements (for extra debug messages.) In
Verilog, the preprocessor was great, since I could directly
activate the macro-define (`define) from the command-line

( example, 'ncverilog my_module.v +define+DBG_MY_MODULE=1;')
VHDL does not have 'define. Use constant/generic with if/if generate
Click to expand...
statements.

The advantage of the VHDL approach is that all your code is analyzed.
Therefore,
it detects syntax errors on *all* your code. With the verilog
approach, you
may have surprises when you define DBG_MY_MODULE.

JD.
 
john Doef wrote:

The advantage of the VHDL approach is that all your code is analyzed.
Therefore,
it detects syntax errors on *all* your code. With the verilog
approach, you
may have surprises when you define DBG_MY_MODULE.
Click to expand...
Yes but IMHO, the pros *FAR* outweigh the cons... :(

It's really, really inconvenient not to have define in VHDL..

Regards,
Mark
 
Von Mark McDougall:

john Doef wrote:

The advantage of the VHDL approach is that all your code is analyzed.
Therefore,
it detects syntax errors on *all* your code. With the verilog
approach, you
may have surprises when you define DBG_MY_MODULE.

Yes but IMHO, the pros *FAR* outweigh the cons... :(

It's really, really inconvenient not to have define in VHDL..
Click to expand...
What? You don't want to edit your code by hand before synthesis to avoid
such stuff?

ERROR:Xst:826
- /local/eike/AFS/Diplom/Code/racebridge/hdl/Bridge_In/Inp_Route.vhdl
line 98: Statement ReportStatement is not supported yet.

Let me think a second. I agree.

Eike
 
Hi I_likes_Verilog,

I've just started learning VHDL, and there is some convenience
feature I need ...

In verilog, I'd often use the (`ifdef) preprocessor to enclose
debugging statements.

`ifdef DBG_MY_MODULE
intial begin
$display("recognized DBG_MY_MODULE!" );
// go spam the console with extra debug messages!
//
//

`endif

In VHDL, I haven't found a way to do this...
Click to expand...
I miss that feature too. As a trick, I tend to use the C preprocessor for
GCC, which I have on my PC anyway. So, I sometimes have

#include <stdinc.vhd>

entity bla is
port (
#ifdef DEBUG
debug_pin : out std_logic_vector(NBITS downto 0);
#endif
clk : in std_logic;
etc etc.

I then run cpp design.vhc design.vhd before compiling. Using make (also
comes with GCC) makes this really easy.

Best regards,


Ben
 
I_likes_Verilog wrote:

Obviously, I can put flag_dbg_my_module in a 'package'.
But is there a more convenient/clever way to do this?
Click to expand...
I prefer to declare a generic constant
to do this sort of thing.

generic (verbose_c : boolean := true);
-- ...
boring : if verbose_c then ...

If you prefer to use a preprocessor, there are many to
choose from. However vhdl does not include one.
That's just the way it is.

I just want some quick and dirty way to 'activate' a
block of statements (for extra debug messages.)
Click to expand...
vsim -Gverbose_c=false my_tb

-- Mike Treseler
 
Ben Twijnstra wrote:

I miss that feature too. As a trick, I tend to use the C preprocessor
for GCC, which I have on my PC anyway. So, I sometimes have
#include <stdinc.vhd
Click to expand...
(snip)

Yeah, if I had *my* way I'd be doing that too! :(

Regards,
Mark
 
Hi,
It is a subject like a cold which shows up several times a month.

I really don't understand why VHDL doesn't include those convenient
features that can be easily implemented and really don't know what is
wrong for some controllers of the language specifications not do that.

Why to use GCC for an independent large language VHDL?

Weng
 
Perhaps this is of interest:

http://klabs.org/richcontent/software_content/kpp.htm

-- rk

Weng Tianxiang wrote:

Hi,
It is a subject like a cold which shows up several times a month.

I really don't understand why VHDL doesn't include those convenient
features that can be easily implemented and really don't know what is
wrong for some controllers of the language specifications not do that.

Why to use GCC for an independent large language VHDL?

Weng
Click to expand...


--
rk, Just an OldEngineer
"These are highly complicated pieces of equipment almost as complicated as
living organisms. In some cases, they've been designed by other computers. We
don't know exactly how they work."
-- Scientist in Michael Crichton's 1973 movie, Westworld
 
You can also look for my EVHDL on www.entner-electronics.com

Thomas

"rk" <stellare@nospamplease.comcast.net> schrieb im Newsbeitrag
news:Xns96E7E0F5A3D25rk@216.196.97.136...
Perhaps this is of interest:

http://klabs.org/richcontent/software_content/kpp.htm

-- rk

Weng Tianxiang wrote:

Hi,
It is a subject like a cold which shows up several times a month.

I really don't understand why VHDL doesn't include those convenient
features that can be easily implemented and really don't know what is
wrong for some controllers of the language specifications not do that.

Why to use GCC for an independent large language VHDL?

Weng




--
rk, Just an OldEngineer
"These are highly complicated pieces of equipment almost as complicated as
living organisms. In some cases, they've been designed by other computers.
We
don't know exactly how they work."
-- Scientist in Michael Crichton's 1973 movie, Westworld
Click to expand...
 
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