VHDL Function Pointers?

Hi,

I'm very new to VHDL and have tried to research a fair amount before
asking if VHDL has the equivalent of a "function pointer type," similar
to the C language.

For example, if I have this code (code doesn't compile, just trying to
convey an idea):

type sim_entity;

type sim_entity_ptr is access sim_entity;

component sim_entity is
port (In1, In2, In3, In4 : in bit;
Out1, Out2, Out3, Out4 : out bit);
end component sim_entity;

type circuitry_component is record
behavior_model : sim_entity_ptr;
end record;

And later in my architecture code, I decide to do something like this:

circuitry_component_ptr.behavior_model
use entity sim_entity(whatever);

circuitry_component_ptr.behavior_mode port map (..);

I realize the code above doesn't work and is not even close, I'm trying
to understand if there is an equivalent way to express either function,
procedure or even component pointers.

Thanks in advance,

 

[Jonathan Bromley]

On 8 Oct 2005 18:02:01 -0700, poopierabbit@yahoo.com wrote:

I'm very new to VHDL and have tried to research a fair amount before
asking if VHDL has the equivalent of a "function pointer type," similar
to the C language.

The simple answer is: No.
Access types can point only to variable-type things.

A more complicated answer:

Function pointers would probably be cool, but they don't exist
in VHDL because of its obsession with compile-time checking.
It is rare indeed to find a situation where you can't
program your way around the lack.

Pointers (references) to instantiated objects (components
or whatever) are a very interesting idea - see, for
example, the "virtual interface" construct in SystemVerilog -
but they have very, very complicated consequences for the
language definition. Once again, no such thing in VHDL.

Don't forget that VHDL was primarily designed for the
description of digital systems. Such things tend to be
built from physical hardware, which has no concept of
dynamic binding or instantiation. The language design
trades off flexibility for a very robust specification
that is a rather good match for many modelling requirements.
If you want flexibility, you have plenty of other choices
--
Jonathan Bromley, Consultant

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