A
Abdelhalim
Guest
Hi,
I'd like to know if there's a statistics for the Usage of the RTL VHDL
features within the VHDL designers, for example. the usage of generate
statement, the usage of exit statement, etc.
If there any, can you point me where ?
Abdelhalim
I'd like to know if there's a statistics for the Usage of the RTL VHDL
features within the VHDL designers, for example. the usage of generate
statement, the usage of exit statement, etc.
If there any, can you point me where ?
Abdelhalim