VHDL events

Hi,

I have just started trying to learn VHDL and I am wondering about the
"event" keyword. If I write:

process(clock)
begin
if clock'event and clock = '1' then

end if
end process;

then I step inside the if statement every rising clock edge. If I do
the opposite:

process(clock)
begin
if clock'event and clock = '0' then

end if
end process;

then do I step inside every falling clock edge? Also, can I do this:

process(clock)
begin
if clock'event and clock = '0' then

elsif clock'event and clock = '1' then

end if
end process;

to do something on the falling and rising clock edges? I remember
seeing a post which said this was bad, but I don't remember why.

Thanks,
David

 

[Jonathan Bromley]

On Tue, 9 Dec 2008 01:35:43 -0800 (PST), no.spam.mole wrote:

if clock'event and clock = '0' then

then do I step inside every falling clock edge?

Yes. clock'event is true whenever the clock has just
changed (strictly, it has changed in the current
delta cycle) and of course it is exactly this event
that caused the process's sensitivity list to trip.
If there has been an event on clock, and its new
value is '0', then it's fairly safe to assume that
there was a falling edge on it. Even safer if you
write

if falling_edge(clock)

Also, can I do this:

process(clock)
begin
if clock'event and clock = '0' then

elsif clock'event and clock = '1' then

end if
end process;

to do something on the falling and rising clock edges? I remember
seeing a post which said this was bad, but I don't remember why.

In simulation, yes, you definitely can. But some
synthesis tools still cannot infer DDR registers from this
code. And, of course, it is foolish to try to do this for
a synthesisable design unless you are certain that you have
some suitable DDR registers for the process to map onto.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Tricky]

On 9 Dec, 09:35, no.spam.m...@googlemail.com wrote:

Hi,

I have just started trying to learn VHDL and I am wondering about the
"event" keyword.  If I write:

process(clock)
begin
   if clock'event and clock = '1' then

  end if
end process;

then I step inside the if statement every rising clock edge.  If I do
the opposite:

process(clock)
begin
   if clock'event and clock = '0' then

  end if
end process;

then do I step inside every falling clock edge?  Also, can I do this:

process(clock)
begin
   if clock'event and clock = '0' then

   elsif clock'event and clock = '1' then

  end if
end process;

to do something on the falling and rising clock edges?  I remember
seeing a post which said this was bad, but I don't remember why.

Thanks,
David

It depends on the architecture you are using. FPGA's wont accept both
edges (I dont know anything about ASICs).

It is perfectly acceptable VHDL, and will simulate as you expect. Just
dont expect it to work in real hardware. Use one edge or the other,
and if you need both edges then just multiply your clock x2

Coincidently, VHDL has 2 functions that are a bit more explicit:
rising_edge(clk) and falling_edge(clk) which you can use in place of
clk'event and clk = '1'/'0';

The problem with clk'event and clk = '1' is that it will be true when
the clock changes from ANYTHING to a '1'
Rising/falling_edge functions are only true when the clk changes from
'0' to '1'.
These functions werent standard until 1993, and so alot of older
examples will use the 'event method.

 

[David Spencer]

"Tricky" <Trickyhead@gmail.com> wrote in message
news:c736ad3d-31a3-4350-8885-2b0fc70a3569@k1g2000prb.googlegroups.com...
On 9 Dec, 09:35, no.spam.m...@googlemail.com wrote:
Rising/falling_edge functions are only true when the clk changes from
'0' to '1'.

Actually, rising_edge() and falling_edge() are more flexible than you
suggest. They will detect changes from anything that is interpreted as low
to anything that is interpreted as high, or vice-versa, meaning that
simulation will match synthesis correctly.

For example, on a wire-ORed clock signal, rising_edge() would correctly
detect a transition from '0' to 'H' whereas the traditional form using
'event wouldn't. Conversely, for example, rising_edge() will correctly not
detect a transition from 'H' to '1' as a valid clock whereas 'event would.

 

[Andy]

On Dec 9, 5:04 am, Tricky <Trickyh...@gmail.com> wrote:

It depends on the architecture you are using. FPGA's wont accept both
edges (I dont know anything about ASICs).

It is perfectly acceptable VHDL, and will simulate as you expect. Just
dont expect it to work in real hardware. Use one edge or the other,
and if you need both edges then just multiply your clock x2

Some synthesis tools will not accept a single process with two edge
detections. Others will, but will not accept assignments to the same
variable or signal on both edges (since that would require a DDR
register).

Perhaps they should, since DDR behavior can be implemented with two
SDR registers and 3 xor (or xnor) gates:

process (clk) is
variable qr, qf : std_logic;
begin
if rising_edge(clk) then
qr := d xor qf; -- registered encode of input
elsif falling_edge(clk) then
qf := d xor qr; -- registered encode of input
end if;
q <= qr xor qf; -- combinatorial decode of output
end process;

This can also be re-written using signals and three processes if
you're synthesis tool does not like a single process for all three
(two clock edges and the combinatorial decode). Note that it does not
necessarily have to be opposite edges of one clock signal. You could
make it work off any two clocks as long as they are locked
synchronously to each other.

For small circuits that need DDR behavior, this is often more
efficient than using a DLL/PLL to double the clock.

Andy