VHDL equivalent of verilog trireg

[Sanjeev]

I would like to know the vhdl equivalent of verilog trireg.

 

[Jonathan Bromley]

On 22 Jul 2004 04:05:46 -0700, sanjeev.chaudhri@gmail.com (Sanjeev)
wrote:

I would like to know the vhdl equivalent of verilog trireg.

Depends how much of the Verilog functionality you need to mimic.

The basic behaviour (hold the last driven value, if all drivers
are floated) is easy to achieve: just drive a weaker version
of the signal's level back on to itself, so it holds its value
if all other drivers on it are driving 'Z'. Here's one
possible implementation, using a lookup table as a cut-price
conversion function (one of my favourite pieces of VHDL
testbench trickery):

[in some package]
type sl_map_table is array(std_ulogic) of std_ulogic;
constant weaken: sl_map_table := (
'U' => 'W',
'X' => 'W',
'0' => 'L',
'1' => 'H',
'Z' => 'W',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => 'W'
);

[declaration]
signal my_trireg: std_logic;

[within the architecture]
my_trireg <= weaken(my_trireg);

If I remember correctly, Verilog trireg can also offer a
"capacitive decay" behaviour in which its value collapses
to X if it hasn't been updated after some specified time.
You can imitate this using VHDL inertial delay:

my_trireg <= weaken(my_trireg), 'W' after decay_time;

None of this makes any sense for synthesis, of course.
You also need to be aware that it puts some constraints
on any other logic connected to the same signal:

1) Drivers must drive '1' or '0', never 'H' or 'L',
so that they can overcome the trireg hold value.
2) Any logic that uses the signal's value must
treat 'H' and 'L' as valid '1' and '0' values.
Verilog deals with this automatically. Likewise,
so do all the std_logic_1164 logic operators:

'H' and '1' = '1'
'L' and '1' = '0'
not 'L' = '1'

But you can get into trouble if you test for
'1' or '0' in an "if" or "case", or use
the equality or comparison operators:

if my_trireg = '1' then ...
-- FAILS if my_trireg = 'H' :-(

if my_trireg > '0' then ...
-- SUCCEEDS if my_trireg = 'L' :-(

Most of these problems can be worked-around by
applying the To_X01() strength stripper whenever
you try to make use of the signal value:

if To_X01(my_trireg) = '1' then ...
-- SUCCEEDS if my_trireg = 'H'

Hope this helps.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On Thu, 22 Jul 2004 13:11:13 +0100, Jonathan Bromley
<jonathan.bromley@doulos.com> wrote:

I would like to know the vhdl equivalent of verilog trireg.

Depends how much of the Verilog functionality you need to mimic.

[snip lots of vaguely sensible ramblings]

If I remember correctly, Verilog trireg can also offer a
"capacitive decay" behaviour in which its value collapses
to X if it hasn't been updated after some specified time.
You can imitate this using VHDL inertial delay:

my_trireg <= weaken(my_trireg), 'W' after decay_time;

Oh dear, oh dear, oh dear. This doesn't work. It's my
faulty memory of something similar, but slightly different.

Today's challenge (1): what's wrong with it?
Today's challenge (2), harder: how to fix it?

I have a wonderful solution, but the margin of this
lunch break is too short to accommodate it
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Allan Herriman]

On Thu, 22 Jul 2004 13:11:13 +0100, Jonathan Bromley
<jonathan.bromley@doulos.com> wrote:

On 22 Jul 2004 04:05:46 -0700, sanjeev.chaudhri@gmail.com (Sanjeev)
wrote:

I would like to know the vhdl equivalent of verilog trireg.

[snip]

None of this makes any sense for synthesis, of course.

I assume that you meant to say that it cannot be inferred by current
synthesis tools.
XST, for example, can generate one from HDL source using the "keeper"
attribute (on an I/O pin only, since Xilinx FPGAs no longer have
internal tristate signals).

(Or were you just referring to the decay effect? If this is the case,
I agree with you.)

Regards,
Allan.

 

[Jonathan Bromley]

On Fri, 23 Jul 2004 13:19:44 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Thu, 22 Jul 2004 13:11:13 +0100, Jonathan Bromley
jonathan.bromley@doulos.com> wrote:

None of this makes any sense for synthesis, of course.

I assume that you meant to say that it cannot be inferred by current
synthesis tools.
XST, for example, can generate one from HDL source using the "keeper"
attribute (on an I/O pin only)

The code I posted is, of course, a "weak keeper" or "bus hold" model.
It was careless of me to say that it makes no sense for synthesis,
since it represents a perfectly reasonable hardware structure;
but I was not aware that any tools could correctly infer such
a structure from the behavioural description. One more gold star
to XST (the first one was for correct handling of initialisation
in the declaration of a flip-flop signal).
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.