VHDL: Different direction buses

[arkaitz]

Hi all,

It might be an obvious question but I have a doubt when assigning two buses
that are defined with opposite direction.

Here you are an example;

architecture behavioral of buses is
signal bus_a: std_logic_vector (0 to 7);
signal bus_b: std_logic_vector (7 downto 0);
...
begin

-- this doesn't work
bus_b <= bus_a;

-- but don't know why this doesn't work
process (bus_a)
begin
for i in bus_a'range loop
bus_b (i) <= bus_a (i)
end loop;

-- this works
process (bus_a)
begin
for i in bus_a'range loop
bus_b(i) <= bus_a (bus_a'left - i);
end loop;
end process;

Does anybody have any idea why the second example doesn't work?

Thanks in advance.

Arkaitz.

 

[Alan Fitch]

Hi all,

It might be an obvious question but I have a doubt when assigning
two buses
that are defined with opposite direction.

Here you are an example;

architecture behavioral of buses is
signal bus_a: std_logic_vector (0 to 7);
signal bus_b: std_logic_vector (7 downto 0);
...
begin

-- this doesn't work
bus_b <= bus_a;

What do you meant "it doesn't work?". It works fine! In
VHDL vectors are assigned left to right, *regardless of how
they are declared*. So that code says

bus_b(7) <= bus_a(0);
bus_b(6) <= bus_a(1);
bus_b(5) <= bus_a(2);
bus_b(4) <= bus_a(3);
bus_b(3) <= bus_a(4);
bus_b(2) <= bus_a(5);
bus_b(1) <= bus_a(6);
bus_b(0) <= bus_a(7);

Which looks fine to me. That's how VHDL works...

-- but don't know why this doesn't work
process (bus_a)
begin
for i in bus_a'range loop
bus_b (i) <= bus_a (i)
end loop;

Again, what do you mean "it doesn't work"?

bus_a'range gives you "0 to 7", so the loop results in

bus_b(0) <= bus_a(0);
bus_b(1) <= bus_a(1);
...
bus_b(7) <= bus_a(7);

which again works fine. Of course it does something different
from your first example...

-- this works
process (bus_a)
begin
for i in bus_a'range loop
bus_b(i) <= bus_a (bus_a'left - i);
end loop;
end process;

This does
bus_b(0) <= bus_a(0-0);
bus_b(1) <= bus_b(0-1); -- error!

so should not run. It should give a "index out of range error".
You may only see that at run time however, not at compile time.

Does anybody have any idea why the second example doesn't work?

I believe your first two examples "work", and the last example doesn't
because of the indexing error.

What exactly are you trying to achieve?

kind regards

Alan



--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

 

[arkaitz]

Upppsss,

I'm sorry. The second example is wrong,


arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0312042308.27180437@posting.google.com>...

Hi all,

It might be an obvious question but I have a doubt when assigning two buses
that are defined with opposite direction.

Here you are an example;

architecture behavioral of buses is
signal bus_a: std_logic_vector (0 to 7);
signal bus_b: std_logic_vector (7 downto 0);
...
begin

-- this doesn't work
bus_b <= bus_a;

-- but don't know why this doesn't work
process (bus_a)
begin
for i in bus_a'range loop
bus_b (i) <= bus_a (i)
end loop;

-- this works
process (bus_a)
begin
for i in bus_a'range loop
bus_b(i) <= bus_a (bus_a'left - i);
bus_b(i) <= bus_a (bus_a'right - i); -- better like this
end loop;
end process;

Does anybody have any idea why the second example doesn't work?

Thanks in advance.

Arkaitz.

 

[arkaitz]

Thanks Alan for the help.

The thing is that I have been looking for it in a manual that mentions
that isn't possible to assign different direction buses in one
instruction.

I've tried and it works, so thanks again.

Best regards,

Arkaitz.

"Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<bqpk9o$p7t$1$8302bc10@news.demon.co.uk>...

Hi all,

It might be an obvious question but I have a doubt when assigning
two buses
that are defined with opposite direction.

Here you are an example;

architecture behavioral of buses is
signal bus_a: std_logic_vector (0 to 7);
signal bus_b: std_logic_vector (7 downto 0);
...
begin

-- this doesn't work
bus_b <= bus_a;



What do you meant "it doesn't work?". It works fine! In
VHDL vectors are assigned left to right, *regardless of how
they are declared*. So that code says

bus_b(7) <= bus_a(0);
bus_b(6) <= bus_a(1);
bus_b(5) <= bus_a(2);
bus_b(4) <= bus_a(3);
bus_b(3) <= bus_a(4);
bus_b(2) <= bus_a(5);
bus_b(1) <= bus_a(6);
bus_b(0) <= bus_a(7);

Which looks fine to me. That's how VHDL works...

-- but don't know why this doesn't work
process (bus_a)
begin
for i in bus_a'range loop
bus_b (i) <= bus_a (i)
end loop;

Again, what do you mean "it doesn't work"?

bus_a'range gives you "0 to 7", so the loop results in

bus_b(0) <= bus_a(0);
bus_b(1) <= bus_a(1);
...
bus_b(7) <= bus_a(7);

which again works fine. Of course it does something different
from your first example...


-- this works
process (bus_a)
begin
for i in bus_a'range loop
bus_b(i) <= bus_a (bus_a'left - i);
end loop;
end process;


This does
bus_b(0) <= bus_a(0-0);
bus_b(1) <= bus_b(0-1); -- error!

so should not run. It should give a "index out of range error".
You may only see that at run time however, not at compile time.

Does anybody have any idea why the second example doesn't work?


I believe your first two examples "work", and the last example doesn't
because of the indexing error.

What exactly are you trying to achieve?

kind regards

Alan



--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.