VHDL design and System Verilog testbench

[rittu]

Hello Everybody,

I am a verification trainee at a company and i am verifying
design made in VHDL through a Systemverilog testbench.There are som
paramters used in the design and I want to force these parameters throug
the test-bench,I cannot use any of the scripting languages,is there an
other way to force these parameters through the test bench??

I have used defparam but no use.

Regards
Ritesh




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Posted through http://www.FPGARelated.com

 

[backhus]

On 27 Apr., 04:06, "rittu" <rittu16@n_o_s_p_a_m.gmail.com> wrote:

Hello Everybody,

              I am a verification trainee at a company and i am verifying a
design made in VHDL through a Systemverilog testbench.There are some
paramters used in the design and I want to force these parameters through
the test-bench,I cannot use any of the scripting languages,is there any
other way to force these parameters through the test bench??

I have used defparam but no use.

Regards
Ritesh

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Hi Ritesh.
are the design parameters in the VHDL files set with "generic"s?
If so it should be simple to use verilog "parameter" statements at the
DUT instantiation to set these values in your testbench.

Have a nice simulation
Eilert