VHDL desciption of BLock RAM

[fpgawizz]

I get this message when i synthesize my code
(This is a design on xilinx Spartan 3 FPGA using Xilinx tools)
"you may be trying to describe a RAM in a way that is incompatible with
block and distributed RAM resources available on xilinx devices, or with a
specific template that is not supported"

I have this signal sram_data which is of type array(0 to 255) of
std_logic_Vector(7 downto 0). I am assigning values to each element
sram_data(N) inside a state machine and this message pops up when i
synthesize.
any comments on how i can fix this?

thanks

 

[fpgawizz]

Neo
Here is th state machine.I am receiving serial data via RS 232 and
sampling teh data. As I sample a byte, I want to write to an external RAM
as well as store it in an ARRAY ( I guess that is my block RAM). The
signal sram_data is used here to store the data in an array. The message I
get when i synthesize is on the sugnal sram_data saying that i am trying
to describe a RAM in a non standard way or a way that XST doesn;t quite
understand.

thanks..
**************************************************

entity DataComm1 is
Port ( clk : in std_logic;
RESET : in std_logic;
Din : in std_logic;
SRAMADDR : out std_logic_vector(7 downto 0);
DATABUS : inout std_logic_vector(7 downto 0);
CE1 : out std_logic;
CE2 : out std_logic;
WE : out std_logic;
OE : out std_logic;
LB : out std_logic;
UB : out std_logic;
LD : out std_logic_vector(7 downto 0));
end Datacomm1;

architecture Behavioral of DataComm1 is

signal clk_6_51u : std_logic := '0';
constant clk_6_51u_count : integer := 163;
type mystate is
(rst,idle,startbit,d0,d1,d2,d3,d4,d5,d6,d7,stopbit,dataready,incN);
signal statevar : mystate := rst;

type memwrite is (IDLE,WRITEADDR,SETUPWRITE,WRITE);
signal varwrite : memwrite := IDLE;

type memory is array(0 to 20) of std_logic_vector(7 downto 0);
signal sram_data : memory;
signal N : integer range 0 to 100;
signal data_ready : std_logic;

signal cnt : integer range 0 to 200;
signal shift_reg : std_logic_vector(15 downto 0);
signal data : std_logic_vector(7 downto 0);
--signal firsttime : integer range 0 to 1;

signal memclk : std_logic := '0';
constant memcnt : integer := 80;

begin

-- generate a 6.510 us clock from the 50 MHz oscillator
clk_6_51u_Process: process(clk)
variable counter_50M : integer range 0 to clk_6_51u_count;

begin
if clk'event and clk = '1' then
counter_50M := counter_50M+1;
if counter_50M = clk_6_51u_count then
clk_6_51u <= NOT clk_6_51u;
counter_50M := 0;
end if;
end if;
end process clk_6_51u_Process;

-- generate a mem clock from the 50 MHz oscillator
MemClk_Process: process(clk)
variable counter_50M : integer range 0 to memcnt;

begin
if clk'event and clk = '1' then
counter_50M := counter_50M+1;
if counter_50M = memcnt then
memclk <= NOT memclk;
counter_50M := 0;
end if;
end if;
end process MemClk_Process;

-- get the data coming in

Receive_Process: Process(clk_6_51u,Din)
variable temp : std_logic;
begin
if RESET = '1' then
statevar <= rst;
elsif clk_6_51u'event and clk_6_51u = '1' then
case statevar is
when rst =>
N <= 0;
statevar <= idle;
when idle =>
data_ready <= '0';
shift_reg <= X"FFFF";
cnt <= 0;
statevar <= startbit;
when startbit =>
data_ready <= '0';
shift_reg <= Din & shift_reg(15 downto 1);
if shift_reg = X"0FFF" then
statevar <= d0;
else
statevar <= startbit;
end if;
when d0 =>
shift_reg <= shift_reg;
data_ready <= '0';
--LD <= "00000000";
cnt <= cnt + 1;
if cnt < (16) then
statevar <= d0;
else
data(0) <= Din;
statevar <= d1;
end if;
when d1 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (32) then
statevar <= d1;
else
data(1) <= Din;
statevar <= d2;
end if;
when d2 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (48) then
statevar <= d2;
else
data(2) <= Din;
statevar <= d3;
end if;
when d3 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (64) then
statevar <= d3;
else data(3) <= Din;
statevar <= d4;
end if;
when d4 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (80) then
statevar <= d4;
else
data(4) <= Din;
statevar <= d5;
end if;
when d5 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (96) then
statevar <= d5;
else
data(5) <= Din;
statevar <= d6;
end if;
when d6 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (112) then
statevar <= d6;
else
data(6) <= Din;
statevar <= d7;
end if;
when d7 =>
shift_reg <= shift_reg;
data_ready <= '0';
cnt <= cnt + 1;
if cnt < (128) then
statevar <= d7;
else
data(7) <= Din;
statevar <= stopbit;
end if;
when stopbit =>
shift_reg <= shift_reg;
cnt <= cnt + 1;
if cnt < (144) then
statevar <= stopbit;
else
temp := Din;
LD <= data;
sram_data(N) <= data;
data_ready <= '0';
statevar <= dataready;
end if;
when dataready =>
data_ready <= '1';
statevar <= incN;
when incN =>
data_ready <= '0';
N <= N + 1;
statevar <= idle;
end case;

end if;

end process Receive_Process;


WriteMem_Process: process(memclk,data_ready)
begin
if memclk'event and memclk = '1' then
case varwrite is
when IDLE =>
CE1 <= '1';
CE2 <= '0';
LB <= '0';
UB <= '1';
SRAMADDRUPPER <= "0000000000";
SRAMADDR <= "00000000";
DATABUS <= "ZZZZZZZZ";
OE <= '0';
WE <= '1';

if data_ready = '1' then
varwrite <= WRITEADDR;
else
varwrite <= IDLE;
end if;
when WRITEADDR =>
SRAMADDR <= conv_std_logic_vector(N,8);

varwrite <= SETUPWRITE;
when SETUPWRITE =>
DATABUS <= sram_data(N);
OE <= '1';
WE <= '0';
varwrite <= WRITE;
when WRITE =>
WE <= '1';
varwrite <= IDLE;
end case;

end if;

end process WriteMem_Process;

end Behavioral;

 

[KCL]

you couldn't use your memory in a process with a reset even if you don't
have anything in the reset
I think it's that your problem try your vhdl without the reset condition

Alexis

if RESET = '1' then
statevar <= rst;
elsif clk_6_51u'event and clk_6_51u = '1' then
case statevar is
....................
sram_data(N) <= data;
......
end case;

end if;

end process Receive_Process;

 

[info_]

Hi,

I very quickly browsed your code and found many things which, imo, don't look very
good (incorrect sensitivity list, multiple & derived clock domains, careless clock
domain crossing, missing set/reset on registers, input not resynchronized, etc...)
Also, in many places you test a signal after incrementing it, I hope you're aware
that the value you are testing is from _before_ the incrementation...
Note also that assignment to self is useless (but it's purely cosmetic, no danger here).
As a result, I suspect that you may encounter other problems later...
Why not take a look at the VHDL Coding Style I just published ?
and avoid creating clock domains if you don't need them (as I suspect).
BTW : your state machine would also gain in clarity if you did factor out default
assignements like for data_ready<='0';

Hope this helps,

Bert Cuzeau

fpgawizz wrote:

I get this message when i synthesize my code
(This is a design on xilinx Spartan 3 FPGA using Xilinx tools)
"you may be trying to describe a RAM in a way that is incompatible with
block and distributed RAM resources available on xilinx devices, or with a
specific template that is not supported"

I have this signal sram_data which is of type array(0 to 255) of
std_logic_Vector(7 downto 0). I am assigning values to each element
sram_data(N) inside a state machine and this message pops up when i
synthesize.
any comments on how i can fix this?

thanks

 

[Neo]

check the way you are writing to the BRAM. or put the state machine
code here.