Guest
Hi,
I'm trying to writing a code suitable for a data memory but I have
some problem with the input decoder and the multiplexer:
- the decoder receives an address as input (std_logic_vector(7 downto
0)) in order to select one of 256 rows of the storage unit,which has
the typical row-column structure. Each row is formed by a 16-bit-
register (flip-flop) I've built the storage unit with e "generate"
command.
- the mux is driven by the same adress and has to choose one of the
256 rows.
The question is:how can I write the code for a mux that can accept as
input 256 16 bit-long std_logic_vector elements?And how can I write
the code for a decoder whose input is an 8 bit-long address?A for-loop
maybe?
I really don't know.
Thanks
Bye
I'm trying to writing a code suitable for a data memory but I have
some problem with the input decoder and the multiplexer:
- the decoder receives an address as input (std_logic_vector(7 downto
0)) in order to select one of 256 rows of the storage unit,which has
the typical row-column structure. Each row is formed by a 16-bit-
register (flip-flop) I've built the storage unit with e "generate"
command.
- the mux is driven by the same adress and has to choose one of the
256 rows.
The question is:how can I write the code for a mux that can accept as
input 256 16 bit-long std_logic_vector elements?And how can I write
the code for a decoder whose input is an 8 bit-long address?A for-loop
maybe?
I really don't know.
Thanks
Bye