vhdl construct problem

[sudip saha]

Hi, <BR>
In my vhdl code, on construct is as follows <BR>
case to_integer(addr) is <p> when to_integer(fifo1_base + fifo_status )=&gt; <p>Where addr is signal of type unsigned(11 downto 0) and fifo1_base and fifo_status is constant of type unsigned(11 downto 0) <p>I tried to compile my code in Cadence tool(ncvhdl) and modelsim. In both the cases it said <BR>
for "when" statement <BR>
expecting a locally static statement. <p>But surprisingly the code got compiled successfully in quartus. <BR>
Where is the problem while trying to compile with cadence and modelsim? I am using vhdl 93 flag.

 

[Jonathan Bromley]

&lt;sudip saha&gt; wrote in
message news:ee81337.-1@WebX.sUN8CHnE...

case to_integer(addr) is
when to_integer(fifo1_base + fifo_status )=
Where addr is signal of type unsigned(11 downto 0)
and fifo1_base and
fifo_status is constant of type unsigned(11 downto 0)
I tried to compile my code in Cadence tool(ncvhdl)
and modelsim. In both the cases it said
for "when" statement expecting a locally static statement.
But surprisingly the code got compiled successfully in quartus.
Where is the problem while trying to compile with
cadence and modelsim? I am using vhdl 93 flag.

Quartus is bending the rules here.

Create another constant:

constant fifo_base_status : integer :=
to_integer(fifo1_base + fifo_status );

and use that in your case statement.

(By the way, this is purely a VHDL question and would be
better directed to comp.lang.vhdl)
--
Jonathan Bromley, Consultant

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