vhdl: compile-time assert?

[ra]

Hi,
I'm defining a component with some generic constants in VHDL. I'd like
to make synthesis fail with an error if the value given to one of the
constants doesn't satisfy some conditions. Is there any way to do this?

Thanks,
RA

 

[Tim Hubberstey]

ra wrote:

Hi,
I'm defining a component with some generic constants in VHDL. I'd like
to make synthesis fail with an error if the value given to one of the
constants doesn't satisfy some conditions. Is there any way to do this?

I haven't tried this myself but something like this *should* work:

entity test is
generic ( a : integer := ...; b : integer := ...);
....
architecture ... test

-- if the result of the calculation is negative, this
-- should cause an error
constant verify : natural := (some function of a and b);

--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[cristian]

Tim Hubberstey <bogus@bogusname.com> wrote in message news:<mqK6d.5527$Du2.4366@edtnps89>...

ra wrote:

Hi,
I'm defining a component with some generic constants in VHDL. I'd like
to make synthesis fail with an error if the value given to one of the
constants doesn't satisfy some conditions. Is there any way to do this?

I haven't tried this myself but something like this *should* work:

entity test is
generic ( a : integer := ...; b : integer := ...);
...
architecture ... test

-- if the result of the calculation is negative, this
-- should cause an error
constant verify : natural := (some function of a and b);

I am not quite sure if you can do what you want to do.
A constant is a data object that is declared in either the entity, the
architecture (declarative part), a process (declarative part), a
block, a procedure, a function or a package. When you declare a data
object of class constant you have to assign a specific value to the
data object and that value can not be changed by any VHDL statement.
The only exception to that rule is when you declare constant in a
package and you do not assign a value in the declaration. But, you do
(have to ) assign a value in the package body. This is what is called
constant deferred declaration.
In resume contant can not get a new value in your code. So, if you are
looking for checking specific conditions, you can use constant value
to be compared with the value you want to check and assign the result
to a boolean for instance.

regards,

cristian

 

[Nicolas Matringe]

cristian a écrit:

Tim Hubberstey <bogus@bogusname.com> wrote in message news:<mqK6d.5527$Du2.4366@edtnps89>...
I haven't tried this myself but something like this *should* work:

entity test is
generic ( a : integer := ...; b : integer := ...);
...
architecture ... test

-- if the result of the calculation is negative, this
-- should cause an error
constant verify : natural := (some function of a and b);


I am not quite sure if you can do what you want to do.

Sure he can.

A constant is a data object that is declared in either the entity, the
architecture (declarative part), a process (declarative part), a
block, a procedure, a function or a package. When you declare a data
object of class constant you have to assign a specific value to the
data object and that value can not be changed by any VHDL statement.

The constant is assigned a value computed on *generic* parameters, i.e.
constants. This is perfectly legal (and works absolutely fine)

I still don't see how this would make syntesis fail but that's another
question )

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

 

[Martin Bishop]

"ra" <ra@ra.com> wrote in message
news:kwJ6d.1$F92.709@news.sjc.globix.net...

I'm defining a component with some generic constants in VHDL. I'd like
to make synthesis fail with an error if the value given to one of the
constants doesn't satisfy some conditions. Is there any way to do this?

The way I check the consistency of generics with each other or with design
assumptions is:

entity ClkPrescaler
is generic (gPrescalerlength : integer := 2;
gPrescalerValue : integer := 1;
...)
port (...);
end ClkPrescaler;

architecture synthesisable of ClkPrescaler
is
subtype tPrescaler is Unsigned (gPrescalerLength-1 downto 0);
constant cPrescalerMaximum : tPrescaler :=
to_unsigned(2**gPrescalerlength-1, gPrescalerLength);
...

begin
...
assert 1 <= gPrescalerValue and gPrescalerValue <= cPrescalerMaximum
report "gPrescalerValue (" & integer'image(gPrescalerValue)
& ") is out of range : 1..2**gPrescalerLength-1 ("
& integer'image(to_integer(cPrescalerMaximum)) & ")"
severity Failure;
...
end synthesisable;

HTH

If you wish to clean up the function soup used to generate integer text,
define some functions.
Sadly, I don't know of a better way - but live in hope of enlightenment.

I know from experience that the above assertion will fire in ModelSim,
Synplicity and LeonardoSpectrum.

However, the assertion doesn't always work in Xilinx XST; based on back to
back testing with ModelSim. gPrescalerValue = 0 -> assertion raised, =
16 -> assertion not raised (erroneous behaviour). Additionally, XST doesn't
output the fancy messages; you get "Assert statement with non static report"
substituted for the error message; so you stick to dumb text. (I'll open a
case with Xilinx regarding these issues; caveat XST).

A broader issue raised, by this and other 'experiences' with tools, is to
question whether it is not time that VHDL grew some
verification/certification test suites (like Ada and C) and if necessary
standardised implementation subsets to define/verify which language features
have been implemented by a tool.

Martin

 

[cristian]

Nicolas Matringe <nicolasmatringe001@numeri-cable.fr> wrote in message news:<415BCB5D.5070207@numeri-cable.fr>...

cristian a écrit:
Tim Hubberstey <bogus@bogusname.com> wrote in message news:<mqK6d.5527$Du2.4366@edtnps89>...
I haven't tried this myself but something like this *should* work:

entity test is
generic ( a : integer := ...; b : integer := ...);
...
architecture ... test

-- if the result of the calculation is negative, this
-- should cause an error
constant verify : natural := (some function of a and b);


I am not quite sure if you can do what you want to do.

Sure he can.


A constant is a data object that is declared in either the entity, the
architecture (declarative part), a process (declarative part), a
block, a procedure, a function or a package. When you declare a data
object of class constant you have to assign a specific value to the
data object and that value can not be changed by any VHDL statement.

The constant is assigned a value computed on *generic* parameters, i.e.
constants. This is perfectly legal (and works absolutely fine)

I still don't see how this would make syntesis fail but that's another
question )

Nicolas, I do agree with you and that is what I refer to in my first
sentence: how to make the synthesis tool to fail. . .