vhdl code

[vick]

library IEEE;
USE ieee.std_logic_1164.ALL;

ENTITY dte IS PORT ( rst,dcr,ri,cd,cts,rxd,data,clk: in std_logic;
dtr,start,rts,txd,out_dte: out std_logic);
END dte;


--INPUT LINES:

--RI: Ring Indicator -> the modem (DCE) alerts the computer of an
incoming call

--CTS: Clear-To-Send -> the DCE informs the DTE that it can transmit
data

--RxD: Received Data -> it contains the received data

--DCR: DCE Ready -> the DCE is ready to operate

--CD: Received signal line detector -> there are data on the RxD line

--OUTPUT LINES:

--DTR: DTE Ready -> the DTE is ready to send/receive data

--RTS: Request-To-Send -> the DTE informs the DCE that it is going to
transmit data

--TxD: Transmitted Data -> it contains the data to be transmitted

--OUT_dte: Output line -> it contains the data received from the DCE
for presentation to the user



ARCHITECTURE dte_arch OF dte IS
TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,
st10,st11,st12,st13,st14,st15,st16,st17,st18,st19,
st20,st21,st22,st23,st24,st25,st26,st27,st28,st29);

SIGNAL present_dte,next_dte:STATE;

BEGIN

processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk)
BEGIN
if rst='0' then --reset logic low asynchronous
present_dte<=st0;
elsif (clk'event and clk='1') then
present_dte<=next_dte; --the clock '1'move next_dte into
present_dte
end if;

dtr <= '1'; -- dte ready must be set in order
for data to transmitted and recieve.
start <= '0'; --default output
rts <= '0';
txd <= '0';
out_dte <= '0';

CASE present_dte IS

WHEN st0 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; -- dte ready must be set in order --for data to
transmitted and --recieve.
IF data = '1' THEN
next_dte <= st1; -- if there data a then go st1
ELSIF ri = '1' THEN
next_dte <= st15; -- if Ring Indicator logic
'1'a ringing signal is being received --from the telephone
line
ELSE
next_dte <= st0; -- no data continue to wait
END IF;

WHEN st1 => dtr <= '1';start <= '1';rts <= '0'; txd <= '0'; out_dte
<= '0'; --start dte
IF cd = '0' THEN
next_dte <= st1; -- wait for Received signal line
detector to detect there are data

ELSE
next_dte <= st2; --'if logic '1' mean Received signal line detect
there are data on --the RxD line
END IF;

WHEN st2 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --dte ready must be set in order --for data to
transmitted and recieve.
IF rxd= '0' THEN
next_dte <= st2; --rxd Received Data logic '1' go st3 logic '0'
continue to wait
ELSE
next_dte <= st3;
END IF;

WHEN st3 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --dte ready must be set in order --for data to
transmitted and recieve.
IF rxd = '0' THEN
next_dte <= st0; --rxd Received Data logic '1' go st4
logic '0' go back to st0
ELSE
next_dte <= st4;
END IF;

WHEN st4 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --dte ready must be set in order --for data to
transmitted and recieve.
IF cd = '1' THEN
next_dte <= st4; -- there are data on the RxD line
ELSE
next_dte <= st5; -- there are no data on rxd line go to st5
END IF;

WHEN st5 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Request-To-Send DTE --informs the DCE that it is
going to transmit data
IF cts = '0' THEN
next_dte <= st5; -- Clear-To-Send DCE informs the DTE that it can
transmit data see if '1'
ELSE --logic'0' mean not clear
next_dte <= st6;
END IF;

WHEN st6 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for --presentation to the
user then
next_dte <= st7; --next_dte to st7

WHEN st7 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Request-To-Send the DTE --informs the DCE that it
is going to transmit data
IF data = '0' THEN
next_dte <= st7; --if data '0' mean wait
ELSE
next_dte <= st8; --if data '1' go to st8
END IF;

WHEN st8 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Transmitted Data
IF data = '0' THEN
next_dte <= st9; --if data '0' data go st9
ELSE
next_dte <= st11; --data '1' continue sent
END IF;

WHEN st9 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Transmitted end Request-To-Send --the DTE informs
the DCE that it is going to transmit data
IF data = '0' THEN
next_dte <= st10; --if data '0' get new data
ELSE
next_dte <= st12; --data '1' continue sent
END IF;

WHEN st10 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for --presentation to the
user and Request-To-Send --the DTE informs the DCE that it is
going to transmit data
next_dte <= st13;

WHEN st11 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Transmitted Data
IF data = '0' THEN
next_dte <= st10; --if data '0' data sent fail
ELSE
next_dte <= st12; --data '1' continue sent
END IF;

WHEN st12 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '1'; --data come in from DCE for presentation to the user
Transmitted -- data to dte
next_dte <= st13;

WHEN st13 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Transmitted Data
IF data = '1' THEN
next_dte <= st8; --if data '1' go st8
ELSE
next_dte <= st14; --if data '0' no data
END IF;

WHEN st14 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --Transmitted end dte ready --must be set in order for
data to transmitted and recieve.
IF cts = '1' THEN
next_dte <= st14; -- ready for another transmission
ELSE
next_dte <= st0; --logic'0' mean busy go back to st0 mean not clear
to sent
END IF;

WHEN st15 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Request-To-Send the DTE informs the DCE that it is going to
transmit data
IF cts = '0' THEN
next_dte <= st15; -- see if it is clear to sent when cts is logic
'0' wait cts logic '1' go --st16
ELSE
next_dte <= st16;
END IF;

WHEN st16 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Request-To-Send the DTE --informs the DCE that it is
going to transmit data and Transmitted Data
IF data = '0' THEN
next_dte <= st19; -- data '0' go st19 data '1' go st17
ELSE
next_dte <= st17;
END IF;

WHEN st17 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Request-To-Send the DTE informs the DCE that it is going
to --transmit data
next_dte <= st18;

WHEN st18 => dtr <= '1';start <= '0';rts <= '1'; txd <= '0'; out_dte
<= '0'; --Request-To-Send the DTE informs the DCE that it is going to
--transmit data
next_dte <= st29;

WHEN st19 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Request-To-Send the DTE --informs the DCE that it is
going to transmit data and Transmitted Data
next_dte <= st20;

WHEN st20 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Request-To-Send the DTE --informs the DCE that it is
going to transmit data and Transmitted Data
next_dte <= st21;

WHEN st21 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Request-To-Send the DTE --informs the DCE that it is
going to transmit data and Transmitted Data
next_dte <= st22;

WHEN st22 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0';--finish transmitted
IF (cd = '1' AND rxd = '1') THEN --Received signal line detector '1'
and Received Data '1' go st23 else wait
next_dte <= st23;
ELSE
next_dte <= st22;
END IF;

WHEN st23 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for presentation to the user
Transmitted -- data to dte
IF rxd = '0' THEN
next_dte <= st24; --Received Data '0' go st24 '1' go st26
ELSE
next_dte <= st26;
END IF;

WHEN st24 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --dte ready must be set in order for data to transmitted and
--recieve.
IF rxd = '0' THEN
next_dte <= st25; --Received Data '0' go st25 '1' go st27
ELSE
next_dte <= st27;
END IF;

WHEN st25 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '0'; --dte ready must be set in order for data to transmitted and
--recieve.
next_dte <= st28;

WHEN st26 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for presentation to the user
IF rxd = '1' THEN
next_dte <= st27; --Received Data '0' go st25 '1' go st27
ELSE
next_dte <= st25;
END IF;

WHEN st27 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for presentation to the user
next_dte <= st28;

WHEN st28 => dtr <= '1';start <= '0';rts <= '0'; txd <= '0'; out_dte
<= '1'; --data come in from DCE for presentation to the user
IF rxd = '1' THEN
next_dte <= st23; --Received Data '1' go st23 '0' go st0
ELSE
next_dte <= st0;
END IF;

WHEN st29 => dtr <= '1';start <= '0';rts <= '1'; txd <= '1'; out_dte
<= '0'; --Transmitted Data
next_dte <= st0; --return to st0

END CASE;

END PROCESS;

END dte_arch;

can anyone please tell me what each part of the state machine is
doing? thank you very much....

 

[Thomas Stanka]

vhdl200@yahoo.com (vick) wrote:

TYPE state IS (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,
st10,st11,st12,st13,st14,st15,st16,st17,st18,st19,
st20,st21,st22,st23,st24,st25,st26,st27,st28,st29);

Don't use state-machines that size with \=2^n defined states.
Otherwise your systhesized logic won't be predictable without knowing
details of the tool you use for synthesis. Especially structural
equivalence will likely fail.

processdte: PROCESS (rst,dcr,ri,cd,cts,rxd,data,clk)

Don't do ever mix clocked and combinatorial processes. Your simulation
results may differ from the logic your synthesis tool generates.

can anyone please tell me what each part of the state machine is
doing? thank you very much....

The first part (if rst=...end if) switchtes the state each clockcycle.
The second part calculates the outputs and nextstate for each state
your fsm is in. The output is a function of the actual state, the next
state is a function of state and input.

bye Thomas