vhdl code

[Rash]

Hi all,
Am from CS background. Currently am doing my project in vhdl. It is
something like designing a face recognition chip using neural
networks.I got some best weights from matlab neural network toolbox.
The thing is now to store these weight values in a RAM.
Can any one help me how can i store these weight values in RAM, what
size i need, how to code it in VHDL

 

[JeppeM53@gmail.com]

On 22 Jan., 11:08, Rash <rashmiv.ni...@gmail.com> wrote:

Hi all,
Am from CS background. Currently am doing my project in vhdl. It is
something like designing a face recognition chip using neural
networks.I got some best weights from matlab neural network toolbox.
The thing is now to store these weight values in a RAM.
Can any one help me how can i store these weight values in RAM, what
size i need, how to code it in VHDL

Hi Rash

I believe your planning to run the rocognition in parallel -
But you must realize that RAM memories normally will only allow you to
access one word/byte at a given moment.
Inside a FPGA (specially Xilinx Spartan and Virtex families) can you
find Block RAMs (each block = 16kbit)
They are able to provide data at 1,2,4,9,18 and 36 bit wide data-
busses - moreover are they Dual-ported.

I you put all those block RAMs in parallel will you be able to process
a quite large portion of your
neural network in parallel. (I believe)

If your able to define RAM as distributed memory (LUT-based) will you
come one step closer to the
true parallel circuit - but the hardware cost will be huge.

hope you found this useful

Jeppe

 

[Rash]

On Jan 23, 3:00 am, "Jeppe...@gmail.com" <Jeppe...@gmail.com> wrote:

On 22 Jan., 11:08, Rash <rashmiv.ni...@gmail.com> wrote:

Hi all,
Am from CS background. Currently am doing my project in vhdl. It is
something like designing afacerecognitionchip using neural
networks.I got some best weights from matlab neural network toolbox.
The thing is now to store these weight values in a RAM.
Can any one help me how can i store these weight values in RAM, what
size i need, how to code it in VHDL

Hi Rash

I believe your planning to run the rocognition in parallel -
But you must realize that RAM memories normally will only allow you to
access one word/byte at a given moment.
Inside a FPGA (specially Xilinx Spartan and Virtex families) can you
find Block RAMs (each block = 16kbit)
They are able to provide data at 1,2,4,9,18 and 36 bit wide data-
busses - moreover are they Dual-ported.

I you put all those block RAMs in parallel will you be able to process
a quite large portion of your
neural network in parallel. (I believe)

If your able to define RAM as distributed memory (LUT-based) will you
come one step closer to the
true parallel circuit - but the hardware cost will be huge.

hope you found this useful

Jeppe

hi Jeppe,
Thank you for your useful information. Do u have any idea of how to
construct a RAM in Simulink.


Thanks
Rash

 

[Tricky]

On 22 Jan, 22:00, "Jeppe...@gmail.com" <Jeppe...@gmail.com> wrote:

On 22 Jan., 11:08, Rash <rashmiv.ni...@gmail.com> wrote:

Hi all,
Am from CS background. Currently am doing my project in vhdl. It is
something like designing a face recognition chip using neural
networks.I got some best weights from matlab neural network toolbox.
The thing is now to store these weight values in a RAM.
Can any one help me how can i store these weight values in RAM, what
size i need, how to code it in VHDL

Hi Rash

I believe your planning to run the rocognition in parallel -
But you must realize that RAM memories normally will only allow you to
access one word/byte at a given moment.
Inside a FPGA (specially Xilinx Spartan and Virtex families) can you
find Block RAMs (each block = 16kbit)
They are able to provide data at 1,2,4,9,18 and 36 bit wide data-
busses - moreover are they Dual-ported.

I you put all those block RAMs in parallel will you be able to process
a quite large portion of your
neural network in parallel. (I believe)

If your able to define RAM as distributed memory (LUT-based) will you
come one step closer to the
true parallel circuit - but the hardware cost will be huge.

hope you found this useful

Jeppe

In altera stratix familiies, the rams are 512bit (1-18 bit words),
4kbit (1-36 bit words) and 512kbit (8-144bit words) in size, and you
get all three types on each chip.