VHDL code of PLL and LVDS-receiver for FLEX10K Altera PLD

[spiderman_astig]

I'm just a beginner VHDL programmer, I don't know the code for a PLL or even LVDS receiver for a PLD. If someone knows about it, please teach me or tell me how can I make it. Code is better coz I'm running out of time. Thanks!

 

[Ray Andraka]

Simulation or synthesis? You can't write VHDL for digital synthesis for these, as they are not purely digital circuits (a digital PLL is different, but that requires a higher clock, and is a digital circuit, but not one for a
beginner). If your device library has these elements, you get them into your design by instantiation. Your device library should have the details. For simulation, it is a matter of writing code to model the analog behaviour to
the extent you need to model these. A simple model might be just a buffer and an inverter for the LVDS, which will give you a logic level output, but not the analog voltages.

spiderman_astig wrote:

I'm just a beginner VHDL programmer, I don't know the code for a PLL or even LVDS receiver for a PLD. If someone knows about it, please teach me or tell me how can I make it. Code is better coz I'm running out of time. Thanks!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Peter]

Thanks for the comment! I look at the function components of the
device I used but unfortunately PLL and LVDS Receiver are not
supported, that's why I'm looking it's code on web. What I really need
most is that a code which can multiply the frequency of the input
clock. For example, I have an input clock wit a freq. of 50 MHz, I
need to have a generated clock with a 7x of the input clock frequency
(350MHz). Does anyone knows how can I implement it on code?

Thanks and best regards!


Ray Andraka <ray@andraka.com> wrote in message news:<40205E02.8C33CAE1@andraka.com>...

Simulation or synthesis? You can't write VHDL for digital synthesis for these, as they are not purely digital circuits (a digital PLL is different, but that requires a higher clock, and is a digital circuit, but not one for a
beginner). If your device library has these elements, you get them into your design by instantiation. Your device library should have the details. For simulation, it is a matter of writing code to model the analog behaviour to
the extent you need to model these. A simple model might be just a buffer and an inverter for the LVDS, which will give you a logic level output, but not the analog voltages.

spiderman_astig wrote:

I'm just a beginner VHDL programmer, I don't know the code for a PLL or even LVDS receiver for a PLD. If someone knows about it, please teach me or tell me how can I make it. Code is better coz I'm running out of time. Thanks!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ray Andraka]

I'm not sure what you mean by not supported? Are they in the device but not supported by the synthesizer?, the implementation tools? or is it not in the device at all. If it is in the device, you can instantiate a black box to get it
through synthesis. If the implementation tools don't support it but it is present in the device, you need to talk to the device vendor (what device are you talking about anyway?).

Generally speaking, a pure digital circuit can't multiply clocks without also using delays or having a faster clock available. Using delays without any kind of feedback is perilous because the delays in most digital devices are not
tightly controlled, and are subject to variations in temperature, supply voltage and process. You can incorporate feedback to select which tap on a tapped delay line is used and then dynamically adjust the delay to keep the multiplied
clock locked to your reference clock, but in order to do so you need a fairly fine delay tap resolution relative to your clock cycle. You generally won't get that in programmable logic because of the magnitude of the LUT and routing
delays (this is basically what a DLL does, by the way). The xilinx DLLs have a delay tap granularity in the low tens of picoseconds, that is the delay difference between adjacent taps is almost 3 orders of magnitude smaller than the
maximum expected clock frequencies. You can build a model of a DLL in vhdl, but your implementation is going to require very careful hand routing to match delays and the relatively large delays are going to mean a very slow max
clock. The DLL code is not real hard (it isn't trivial either), but for all practical purposes, it is not implementable in programmable devices.

Instead, if your device does not have a clock multiplier circuit, use a faster clock, or use an external PLL chip to generate your clocks.

Peter wrote:

Thanks for the comment! I look at the function components of the
device I used but unfortunately PLL and LVDS Receiver are not
supported, that's why I'm looking it's code on web. What I really need
most is that a code which can multiply the frequency of the input
clock. For example, I have an input clock wit a freq. of 50 MHz, I
need to have a generated clock with a 7x of the input clock frequency
(350MHz). Does anyone knows how can I implement it on code?

Thanks and best regards!

Ray Andraka <ray@andraka.com> wrote in message news:<40205E02.8C33CAE1@andraka.com>...
Simulation or synthesis? You can't write VHDL for digital synthesis for these, as they are not purely digital circuits (a digital PLL is different, but that requires a higher clock, and is a digital circuit, but not one for a
beginner). If your device library has these elements, you get them into your design by instantiation. Your device library should have the details. For simulation, it is a matter of writing code to model the analog behaviour to
the extent you need to model these. A simple model might be just a buffer and an inverter for the LVDS, which will give you a logic level output, but not the analog voltages.

spiderman_astig wrote:

I'm just a beginner VHDL programmer, I don't know the code for a PLL or even LVDS receiver for a PLD. If someone knows about it, please teach me or tell me how can I make it. Code is better coz I'm running out of time. Thanks!

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759