vhdl code in verilog

[uche]

Hi all,

I have a vhdl code that I want to call from a verilog code. How can I
do this?

Thanks,
Uchenna

 

[Mike Treseler]

uche wrote:

I have a vhdl code that I want to call from a verilog code. How can I
do this?

Mixed synthesis is easy for FPGAs.
Mixed simulation costs extra.

-- Mike Treseler
details:
http://www.google.com/search?q=vhdl+verilog+mixed+design

 

[Homuncilus]

On May 1, 3:22 am, uche <uraniumore...@hotmail.com> wrote:

Hi all,

I have a vhdl code that I want to call from a verilog code. How can I
do this?

Thanks,
Uchenna

Hi, uche
Frist, you should create a new verilog module named the same name
of your VHDL module name. And in this verilog module, call the VHDL
module only. Note that all the ports of the verilog module must be
same as the VHDL module's port you called.
Then you can use the VHDL module by calling the verilog module in
your design.

 

On May 1, 6:12 am, Homuncilus <Sha.Cr...@gmail.com> wrote:

On May 1, 3:22 am, uche <uraniumore...@hotmail.com> wrote:

Hi all,

I have a vhdl code that I want to call from a verilog code. How can I
do this?

Thanks,
Uchenna

Hi, uche
Frist, you should create a new verilog module named the same name
of your VHDL module name. And in this verilog module, call the VHDL
module only. Note that all the ports of the verilog module must be
same as the VHDL module's port you called.
Then you can use the VHDL module by calling the verilog module in
your design.

It is absolutely not necessary to create a wrapper like that.

If you want to instantiate a VHDL entity as a Verilog module, you
"just do it", providing your tool supports mixed language.

For example, this VHDL entity:

entity my_dff is
port (
C : in std_ulogic;
R : in std_ulogic;
D : in std_ulogic;
Q : out std_ulogic);
end my_dff;

Can be instantiated in Verilog like this:

my_dff flip_flop (
.c(clock),
.r(reset),
.d(in_net),
.q(out_net)
);


Creating a module wrapper adds an unnecessary layer to hierarchy,
making debugging just that much harder.

G.

 

[gabor]

On May 1, 11:52 am, ghel...@lycos.com wrote:

On May 1, 6:12 am, Homuncilus <Sha.Cr...@gmail.com> wrote:



On May 1, 3:22 am, uche <uraniumore...@hotmail.com> wrote:

Hi all,

I have a vhdl code that I want to call from a verilog code. How can I
do this?

Thanks,
Uchenna

Hi, uche
Frist, you should create a new verilog module named the same name
of your VHDL module name. And in this verilog module, call the VHDL
module only. Note that all the ports of the verilog module must be
same as the VHDL module's port you called.
Then you can use the VHDL module by calling the verilog module in
your design.

It is absolutely not necessary to create a wrapper like that.

If you want to instantiate a VHDL entity as a Verilog module, you
"just do it", providing your tool supports mixed language.

For example, this VHDL entity:

entity my_dff is
port (
C : in std_ulogic;
R : in std_ulogic;
D : in std_ulogic;
Q : out std_ulogic);
end my_dff;

Can be instantiated in Verilog like this:

my_dff flip_flop (
.c(clock),
.r(reset),
.d(in_net),
.q(out_net)
);

Creating a module wrapper adds an unnecessary layer to hierarchy,
making debugging just that much harder.

G.

Just be careful about port names. In Verilog they are case-sensitive
even if they are not case-sensitive in VHDL. So the above example
may not work depending on whether case was retained during VHDL
synthesis. If you use XST for Xilinx FPGA's for instance, the
port names need to match case. You also get very cryptic messages
if they don't match or if the types or vector sizes don't match.
Some other synthesis tools may translate VHDL names to lower case.

I think the point of making a module wrapper is to allow separate
synthesis of the VHDL portion of your project. In Xilinx for
example you would build the VHDL as a standalone project
without the option to create IO's from the top level ports.
Then the .ngc file created this way would be used by the
verilog wrapper. I have done this in the past, but only to
work around bugs in the mixed-language synthesis of XST.

Regards,
Gabor