VHDL code for CIC filters

[Sudhir]

Hi

At the moment we are doing a project to implement all the blocks of DDC
on FPGA.I have been assigned the task for writing a VHDL code for the
cic filter...could anyone out there give me an insight as to where I
should begin???

I have basic knowledge of VHDL and matlab...also I have a general idea
on what the CIC filter consists of and how it works.The problem is that
I don't have the knowledge of relating the working of the CIC filter
and writing a vhdl code for it!!!

Please help!

Thanks Sudhir!

 

[Reiner Huober]

I have basic knowledge of VHDL and >matlab...also I have a general idea
on what the CIC filter consists of and how it >works.The problem is that
I don't have the knowledge of relating the working >of the CIC filter
and writing a vhdl code for it!!!

A CIC filter is just a shift register with an adder/subtractor at the
end. I suggest you begin with a clock and reset signal, add a signal
array, shift the values at every clock and at last the
adder/subtractor.

Details will be in every textbook of VHDL

Hubble.

 

Sudhir wrote:

Hi

At the moment we are doing a project to implement all the blocks of DDC
on FPGA.I have been assigned the task for writing a VHDL code for the
cic filter...could anyone out there give me an insight as to where I
should begin???

I have basic knowledge of VHDL and matlab...also I have a general idea
on what the CIC filter consists of and how it works.The problem is that
I don't have the knowledge of relating the working of the CIC filter
and writing a vhdl code for it!!!

Please help!

Thanks Sudhir!

What FPGA are you using? The Xilinx CoreGenerator can create DDC and
CIC filters.

The book "Digital Signal Processing with Field Programmable Gate
Arrays" does a good job of discussing the implementation of them in
both Verilog and VHDL.

http://www.amazon.com/gp/product/3540211195/qid=1139092453/sr=1-3/ref=sr_1_3/103-5426372-2305419?s=books&v=glance&n=283155

Regards,
John McCaskill

 

[Sudhir]

Thanx for the replies...We are using the spartan IIe fpga. And we are
actually trying to build each and every block of the DDC individually
wihout the use of any coregens!!! Anyways Will try to get hold of the
book as soon as possible!!!