Guest
Hi,
Does anyone know of a tool which will import a set of VHDL design files
and produce a block diagram showing the component interconnections
(without any RTL
translation unlike Xilinx ISE schematic viewer) ?
Thanks
Does anyone know of a tool which will import a set of VHDL design files
and produce a block diagram showing the component interconnections
(without any RTL
translation unlike Xilinx ISE schematic viewer) ?
Thanks