E
Espen Tallaksen
Guest
UVVM - the new VHDL verification methodology is a very good way to structure your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectures.
UVVM is free and open source, and now a whole set of BFMs and Verification Components are also available - open source and for free. This allows a very fast kick-off for new users of UVVM, and of course a really good start for any VHDL testbench development. They also serve as examples on how users can make their own BFMs and VVCs. In fact - if you have already made your BFM procedures for your proprietary protocol - you can make a VVC for that interface in 15 to 60 minutes.
Spend 5 minutes to read our post
'Advanced VHDL Verification - Made simple - For anyone'
https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=mp-author-card, and see for your self how UVVM will allow far better and more structured testbenches to be implemented far faster than before.
(Includes picture, so can't be posted here)
UVVM is free and open source, and you can use it for anything you like, with no restrictions other than the standard MIT open source license.
UVVM is available from github.com and bitvis.no (released in February 2016).
Note that advanced randomization and coverage is available with UVVM via the included OSVVM or adapted UVVM-OSVVM.
Available BFMs and VVCs (VHDL Verification Components) are:
- AXI4-Lite
- Avalon-MM (Single access so far)
- SBI: Simple Bus Interface (Single cycle, optional ready - very simple bus interface)
- UART
- I2C
- SPI (coming in June)
- GPIO (coming in June)
As UVVM takes off we expect the VHDL community will make more BFMs and VVCs available.
UVVM is free and open source, and now a whole set of BFMs and Verification Components are also available - open source and for free. This allows a very fast kick-off for new users of UVVM, and of course a really good start for any VHDL testbench development. They also serve as examples on how users can make their own BFMs and VVCs. In fact - if you have already made your BFM procedures for your proprietary protocol - you can make a VVC for that interface in 15 to 60 minutes.
Spend 5 minutes to read our post
'Advanced VHDL Verification - Made simple - For anyone'
https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=mp-author-card, and see for your self how UVVM will allow far better and more structured testbenches to be implemented far faster than before.
(Includes picture, so can't be posted here)
UVVM is free and open source, and you can use it for anything you like, with no restrictions other than the standard MIT open source license.
UVVM is available from github.com and bitvis.no (released in February 2016).
Note that advanced randomization and coverage is available with UVVM via the included OSVVM or adapted UVVM-OSVVM.
Available BFMs and VVCs (VHDL Verification Components) are:
- AXI4-Lite
- Avalon-MM (Single access so far)
- SBI: Simple Bus Interface (Single cycle, optional ready - very simple bus interface)
- UART
- I2C
- SPI (coming in June)
- GPIO (coming in June)
As UVVM takes off we expect the VHDL community will make more BFMs and VVCs available.