VHDL Beginner: Reset a counter (instead of "000000000....000

[Martin Maurer]

Hello,

i have a counter which is 27 bit long.

signal counter : STD_LOGIC_VECTOR(26 downto 0);

Is there a "better" way to reset than counter <= "00000000...00000" ?
Something like counter <= 0 (26 downto 0) or counter <= 0 ?

Regards,

Martin

 

[Jason Berringer]

Martin,

If your signal "counter" is declared as an integer with a valid range you
can then use a reset as shown:

signal counter : integer range 0 to 67108863 := 0;
....
if reset = '0' then
signal counter <= 0;
....

Another method if you are using standard logic vectors is
....
if reset = '0' then
signal counter <= (others => '0');
....

Hope that this helps,

Jason




".Martin Maurer" <capiman@clibb.de> wrote in message
news:c7m4vd$m5d$05$1@news.t-online.com...

Hello,

i have a counter which is 27 bit long.

signal counter : STD_LOGIC_VECTOR(26 downto 0);

Is there a "better" way to reset than counter <= "00000000...00000" ?
Something like counter <= 0 (26 downto 0) or counter <= 0 ?

Regards,

Martin

 

[Allan Herriman]

On Sun, 9 May 2004 22:40:10 +0200, "Martin Maurer" <capiman@clibb.de>
wrote:

Hello,

i have a counter which is 27 bit long.

signal counter : STD_LOGIC_VECTOR(26 downto 0);

Is there a "better" way to reset than counter <= "00000000...00000" ?
Something like counter <= 0 (26 downto 0) or counter <= 0 ?

counter <= (others => '0');

This is in the comp.lang.vhdl FAQ,
http://www.vhdl.org/comp.lang.vhdl/
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors

Regards,
Allan.

 

[jtw]

Allan & Jason B. show the typical ways; alternatively, if you are using
numeric_std, you could write:

counter <= std_logic_vector(to_unsigned(0,27));

I have found this format useful on occasion where I want to load a constant
that is not all 0's or all 1s.

Jason T. Wright

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:3fot909ludqtgfrf8r9q7bs09p29fbqssm@4ax.com...

On Sun, 9 May 2004 22:40:10 +0200, "Martin Maurer" <capiman@clibb.de
wrote:

Hello,

i have a counter which is 27 bit long.

signal counter : STD_LOGIC_VECTOR(26 downto 0);

Is there a "better" way to reset than counter <= "00000000...00000" ?
Something like counter <= 0 (26 downto 0) or counter <= 0 ?


counter <= (others => '0');

This is in the comp.lang.vhdl FAQ,
http://www.vhdl.org/comp.lang.vhdl/
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#const_vectors

Regards,
Allan.

 

[Martin Thompson]

"jtw" <wrightjt @hotmail.invalid> writes:

Allan & Jason B. show the typical ways; alternatively, if you are using
numeric_std, you could write:

counter <= std_logic_vector(to_unsigned(0,27));

Personally, if I'm doing a counter I would use an unsigned type (or
even an integer!) rather than "casting" to std_logic_vector all the
time. After all, what you're representing is a number...

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

 

[Rajeev]

Hi,

Here's a different but similar question: Is there a better way to do
the following (vector extension):

signal A,B: std_logic_vector(10 downto 0);
signal X: std_logic_vector( 7 downto 0);

A <= "000" & X; -- sometimes I use this

B <= (others => '0'); -- I've also tried this
B(7 downto 0) <= X;

Regards,
-rajeev-
-----------------------
"jtw" <wrightjt @hotmail.invalid> wrote in message news:<e2Xnc.7079$D17.4291@newssvr27.news.prodigy.com>...

Allan & Jason B. show the typical ways; alternatively, if you are using
numeric_std, you could write:

counter <= std_logic_vector(to_unsigned(0,27));

I have found this format useful on occasion where I want to load a constant
that is not all 0's or all 1s.

Thanks for the tip. Handy indeed.

Jason T. Wright

<...>

 

[Michael Schöberl]

A <= "000" & X; -- sometimes I use this

B <= (others => '0'); -- I've also tried this
B(7 downto 0) <= X;

I don't like the second description because in many cases
it is NOT obvious that there is a default value ...

Imagine someone who inserts something else between
the "B" lines ... I've seen this in larger processes (default-values
at the beginning and some declarations later on) ...
not very easy to read ... :-(


bye,
Michael

 

[Ray Andraka]

And historically, some synthesis tools choked on B, although I don't
think there are any that will balk at it now.

Michael Schöberl wrote:

A <= "000" & X; -- sometimes I use this

B <= (others => '0'); -- I've also tried this
B(7 downto 0) <= X;

I don't like the second description because in many cases
it is NOT obvious that there is a default value ...

Imagine someone who inserts something else between
the "B" lines ... I've seen this in larger processes (default-values
at the beginning and some declarations later on) ...
not very easy to read ... :-(

bye,
Michael

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
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