VHDL-beginner question: output-value isn't stored

M

Manfred Balik

Guest
I want to build an easy decode-logic in VHDL.
My problem is that the value I write to the output isn't stored till it
should change :-(
Here my simplified code:

testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
END IF;
END PROCESS testprocess;

The Logic works like:
If IN1=1 and IN2=0 the Output is 1 -> OK :)
If IN1 and IN2 are both 0 the value of the Output is not stored (like I
want) but it goes to zero :-((((
but it should store the 1 till IN1=0 and IN0=1 !!!!

My Design Software Altera Quartus II 5.0 shows this warnings:

Warning: VHDL Process Statement warning at block_name.vhd(54): signal or
variable "OUT0" may not be assigned a new value in every possible path
through the Process Statement. Signal or variable "OUT0" holds its previous
value in every path with no new value assignment, which may create a
combinational loop in the current design.
Critical Warning: Design Assistant warning: Design should not contain
combinational loops. Found 1 combinational loop(s) related to this rule.

If I use a clock in the Process it works like a want it to do, but I don't
want to use a clock!
How must the code look like???
Is a process-statement not the correct choice in VHDL???

please help, Manfred
 
"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message
news:42d22886$0$28520$3b214f66@tunews.univie.ac.at...
I want to build an easy decode-logic in VHDL.
My problem is that the value I write to the output isn't stored till it
should change :-(
Here my simplified code:

testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
END IF;
END PROCESS testprocess;

The Logic works like:
If IN1=1 and IN2=0 the Output is 1 -> OK :)
If IN1 and IN2 are both 0 the value of the Output is not stored (like I
want) but it goes to zero :-((((
but it should store the 1 till IN1=0 and IN0=1 !!!!

My Design Software Altera Quartus II 5.0 shows this warnings:

Warning: VHDL Process Statement warning at block_name.vhd(54): signal or
variable "OUT0" may not be assigned a new value in every possible path
through the Process Statement. Signal or variable "OUT0" holds its
previous
value in every path with no new value assignment, which may create a
combinational loop in the current design.
Critical Warning: Design Assistant warning: Design should not contain
combinational loops. Found 1 combinational loop(s) related to this rule.

If I use a clock in the Process it works like a want it to do, but I don't
want to use a clock!
How must the code look like???
Is a process-statement not the correct choice in VHDL???

please help, Manfred
Click to expand...
Hi,

Your code seems ok. But the compiler complains about combinatorial loops.
Are you feeding the output back to one of the inputs?

Regards,
Alvin.
 
"Alvin Andries"
<Alvin_Andries.dontusethispart@nowhere.agilent.remove_this_too.com> schrieb
im Newsbeitrag news:1121073063.355842@cswreg.cos.agilent.com...
"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message
news:42d22886$0$28520$3b214f66@tunews.univie.ac.at...
I want to build an easy decode-logic in VHDL.
My problem is that the value I write to the output isn't stored till it
should change :-(
Here my simplified code:

testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
END IF;
END PROCESS testprocess;

The Logic works like:
If IN1=1 and IN2=0 the Output is 1 -> OK :)
If IN1 and IN2 are both 0 the value of the Output is not stored (like I
want) but it goes to zero :-((((
but it should store the 1 till IN1=0 and IN0=1 !!!!

My Design Software Altera Quartus II 5.0 shows this warnings:

Warning: VHDL Process Statement warning at block_name.vhd(54): signal or
variable "OUT0" may not be assigned a new value in every possible path
through the Process Statement. Signal or variable "OUT0" holds its
previous
value in every path with no new value assignment, which may create a
combinational loop in the current design.
Critical Warning: Design Assistant warning: Design should not contain
combinational loops. Found 1 combinational loop(s) related to this rule.

If I use a clock in the Process it works like a want it to do, but I
don't
want to use a clock!
How must the code look like???
Is a process-statement not the correct choice in VHDL???

please help, Manfred


Hi,

Your code seems ok. But the compiler complains about combinatorial loops.
Are you feeding the output back to one of the inputs?

Regards,
Alvin.


no feedback, just two inputs and one output !!!!
Click to expand...

Quartus generates following equations:
(looks a little bit complicated for this simple function !!!!????)

--B1L2 is block_name:inst|testprocess~46 at LC2
B1L2_or_out = IN2;
B1L2 = IN1 $ B1L2_or_out;

--B1L1 is block_name:inst|OUT0~10 at LC1
B1L1_p1_out = B1L2 & IN1 & !IN2;
B1L1_p2_out = !B1L2 & B1L1;
B1L1_p3_out = B1L1 & IN1 & !IN2;
B1L1_or_out = B1L1_p1_out # B1L1_p2_out # B1L1_p3_out;
B1L1 = B1L1_or_out;

--IN1 is IN1 at PIN_41
--operation mode is input
IN1 = INPUT();

--IN2 is IN2 at PIN_4
--operation mode is input
IN2 = INPUT();

--OUT0 is OUT0 at PIN_12
--operation mode is output
OUT0 = OUTPUT(B1L1);
 
thank you for that explanation,
but how can I realize the needed function?
not at all withVHDL in a FPGA or CPLD???

Manfred

"Nicolas Matringe" <nic_o_mat@msn.com> schrieb im Newsbeitrag
news:1121076662.600774.266050@g47g2000cwa.googlegroups.com...
no feedback, just two inputs and one output !!!!

The feedback is implicit, as if you had written:
testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
else
OUT0 <= OUT0;
END IF;
END PROCESS testprocess;

What you want is a latch (an RS-latch, actually). Unfortunately for
you, FPGAs don't have latches, they only have flip-flops so QuartusII
tried to implement this using combinatorial logic.

Nicolas
Click to expand...
 
I want to use an Altera MAX 7000 - in the datasheet there is nothing about
"asynchronous latch" :-(
Manfred

"Nicolas Matringe" <nic_o_mat@msn.com> schrieb im Newsbeitrag
news:1121087907.166935.321540@g49g2000cwa.googlegroups.com...
thank you for that explanation,
but how can I realize the needed function?
not at all withVHDL in a FPGA or CPLD???

You already did it with VHDL but you also have to consider your target
(CPLD or FPGA).
Check in the datasheets to see if the components allow you to use an
asynchronous latch instead of a synchronous flip-flop. What you may
need to do though is to rewrite your VHDL to match a template the
synthesis tool will recognize, such as:

process (le, d)
begin
if le = '0' then
q <= d;
end if;
end process;

What is your target component?
(you may want to ask this question in comp.arch.fpga too)

Nicolas
Click to expand...
 
Manfred Balik wrote:

I want to build an easy decode-logic in VHDL.
My problem is that the value I write to the output isn't stored till it
should change :-(
Here my simplified code:

testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
END IF;
END PROCESS testprocess;

The Logic works like:
If IN1=1 and IN2=0 the Output is 1 -> OK :)
If IN1 and IN2 are both 0 the value of the Output is not stored (like I
want) but it goes to zero :-((((
Click to expand...
It seems to be, that you are trapped by the "muxed latch" problem: You
modeled a latch having a mux at it's input. The latch-enable is derived
from the same condition like the mux-selector. Therefore it may be, that
the latch has no yet been closed (because of internal delays) while the
mux already changes it's output.

-> If you are using latches in your circuit, be careful, that the
latch-input is stable while turning the latch off.

-> Latches are small and good for low-power design, but hard to handle.
Especially FPGAs make trouble implementing latches. Think about a
synchronous design using fliplops (sensitive to the edge of a clock).



Warning: VHDL Process Statement warning at block_name.vhd(54): signal or
variable "OUT0" may not be assigned a new value in every possible path
through the Process Statement.
Click to expand...
-> The synthesis tool tells you, that a latch will be inferred.

Signal or variable "OUT0" holds its previous
value in every path with no new value assignment, which may create a
combinational loop in the current design.
Critical Warning: Design Assistant warning: Design should not contain
combinational loops. Found 1 combinational loop(s) related to this rule.
Click to expand...
Is your target capable of handling latches? Some FPGAs implement latchs
as combinational logic with feedback -> "combinational loops".


If I use a clock in the Process it works like a want it to do, but I don't
want to use a clock!
Click to expand...
Why?
If you are shure, that a latch is a good solution - take it and be aware
of the harder way to implement it. Otherwise: Fully synchronous logic is
preferrable.


Ralf
 
Manfred Balik wrote:
I want to use an Altera MAX 7000 - in the datasheet there is nothing about
"asynchronous latch" :-(
Click to expand...
CPLDs and FPGAs are a big array of

=[gates]=[DQ]=

To make best use of such devices
write synthesis code as Ralf advised
in another thread:

process(reset,clock)
begin
if (reset = '1') then
-- do some reset
elsif rising_edge(clock) then
-- one or more if, case etc


-- Mike Treseler
 
no feedback, just two inputs and one output !!!!
Click to expand...
The feedback is implicit, as if you had written:
testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
else
OUT0 <= OUT0;
END IF;
END PROCESS testprocess;

What you want is a latch (an RS-latch, actually). Unfortunately for
you, FPGAs don't have latches, they only have flip-flops so QuartusII
tried to implement this using combinatorial logic.

Nicolas
 
thank you for that explanation,
but how can I realize the needed function?
not at all withVHDL in a FPGA or CPLD???
Click to expand...
You already did it with VHDL but you also have to consider your target
(CPLD or FPGA).
Check in the datasheets to see if the components allow you to use an
asynchronous latch instead of a synchronous flip-flop. What you may
need to do though is to rewrite your VHDL to match a template the
synthesis tool will recognize, such as:

process (le, d)
begin
if le = '0' then
q <= d;
end if;
end process;

What is your target component?
(you may want to ask this question in comp.arch.fpga too)

Nicolas
 
add a clock, then type
wait until clk'event and clk='1';
at the beginning of the process and get rid of the sensitivity list
(the bracket with the input signals). This will use a register to store
the output in a flip-flop and only change it under the conditions you
mention i.e IN1,IN2 = 10 or 01. Bear in mind that transitions will then
only occur on rising edges of the clock. Another trickier way without
using synchronous logic is to create a combinatorial loop using a
multiplexer with inputs OUT0, 0, 1 OUT0, selection bits IN1 and IN2 and
output OUT0. That way, when the selection isnt one of the explicit ones
the output will be the output (doh!). I would think however that this
is very very bad practice. Hope this helps
 
Manfred Balik wrote:
I want to build an easy decode-logic in VHDL.
My problem is that the value I write to the output isn't stored till it
should change :-(
Here my simplified code:

testprocess : PROCESS (IN1,IN2)
BEGIN
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSIF (IN1 = '0') AND (IN2 = '1') THEN
OUT0 <= '0';
END IF;
END PROCESS testprocess;

The Logic works like:
If IN1=1 and IN2=0 the Output is 1 -> OK :)
If IN1 and IN2 are both 0 the value of the Output is not stored (like I
want) but it goes to zero :-((((
but it should store the 1 till IN1=0 and IN0=1 !!!!

My Design Software Altera Quartus II 5.0 shows this warnings:

Warning: VHDL Process Statement warning at block_name.vhd(54): signal or
variable "OUT0" may not be assigned a new value in every possible path
through the Process Statement. Signal or variable "OUT0" holds its previous
value in every path with no new value assignment, which may create a
combinational loop in the current design.
Critical Warning: Design Assistant warning: Design should not contain
combinational loops. Found 1 combinational loop(s) related to this rule.

If I use a clock in the Process it works like a want it to do, but I don't
want to use a clock!
How must the code look like???
Is a process-statement not the correct choice in VHDL???

please help, Manfred
Click to expand...
Manfred,

IN1 and IN2 have a total of 4 values:
IN1 IN2
0 0
0 1 -- your code
1 0 -- your code
1 1
Your code only accounts for 2 values. This results in the compiler
creating a latch for OUT0. The VHDL compiler is telling you this when
it says: "..Signal or variable "OUT0" holds its previous value.."

I am assuming that because this is a decoder, OUT0 does _not_ need to
be latched, so a simple solution is:

testprocess : PROCESS (IN1,IN2)
BEGIN
-- OUT0 is assigned '1' _ONLY_ when IN1 is '1' and IN2 is '0',
-- otherwise, OUT0 is asigned '0'
IF (IN1 = '1') AND (IN2 = '0') THEN
OUT0 <= '1';
ELSE
OUT0 <= '0';
END IF;
END PROCESS testprocess;

HTH,
Dave Pollum
 
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