B
Boki
Guest
Hi, All:
I need to design a decimation filter in VHDL / Verilog, and convert VHDL
code to layout.
I have already design a sigma-delta modulator for 4 KHz input signal, 1.040
MHz sampling frequency in switched-capacitor architecture, and the OSR is
about 128.
I have many questions need your help:
1. How to convert VHDL / Verilog code to layout (*.db/ *.gds file), I mean
the auto-layout process by programs, is there only Verilog code to layout
way?
2. Could you please give me some ideas in decimation filter design,
especially in low-voltage low-power, in my system design, there is only 1-V
supply voltage.
Other questions:
If I already know the close/near harmonic/noise tone to signal point, could
I design a perfect decimation filter to archive a good system?
For a fully-differential sigma-delta modulator system, how to get inverse
signals for fully-differential inputs?
For single-ended system design, does the operation amplifier input offset
voltage decide the system fail?
Do you usually separate clock / comparator / switch / ĄK power line
independently?
Is it is possible to use mos as capacitor for switched-capacitor
architecture?
Thank you very much!
Best regards,
Boki.
I need to design a decimation filter in VHDL / Verilog, and convert VHDL
code to layout.
I have already design a sigma-delta modulator for 4 KHz input signal, 1.040
MHz sampling frequency in switched-capacitor architecture, and the OSR is
about 128.
I have many questions need your help:
1. How to convert VHDL / Verilog code to layout (*.db/ *.gds file), I mean
the auto-layout process by programs, is there only Verilog code to layout
way?
2. Could you please give me some ideas in decimation filter design,
especially in low-voltage low-power, in my system design, there is only 1-V
supply voltage.
Other questions:
If I already know the close/near harmonic/noise tone to signal point, could
I design a perfect decimation filter to archive a good system?
For a fully-differential sigma-delta modulator system, how to get inverse
signals for fully-differential inputs?
For single-ended system design, does the operation amplifier input offset
voltage decide the system fail?
Do you usually separate clock / comparator / switch / ĄK power line
independently?
Is it is possible to use mos as capacitor for switched-capacitor
architecture?
Thank you very much!
Best regards,
Boki.