VHDL attributes equivalent

[BlueDoze]

I'd like to know the verilog equivalent to the following vhdl code.


entity myEntn is
port ( input : in bit_vector ( 16 downto 1);
output1 : out integer;
output2 : out integer;
output3 : out integer
);
end MyEntn;

architecture Arch of MyEntn is
begin
process ( input )
begin
output1 <= input'left;
output2 <= input'right;
output3 <= input'length;
end process;
end;


Regards,

 

[Jonathan Bromley]

"BlueDoze" <bluedoze@yahoo.com> wrote in message
news:a53ecee3.0402190342.7f52719e@posting.google.com...

I'd like to know the verilog equivalent to the following vhdl code.

entity myEntn is
port ( input : in bit_vector ( 16 downto 1);
output1 : out integer;
output2 : out integer;
output3 : out integer
);
end MyEntn;

architecture Arch of MyEntn is
begin
process ( input )
begin
output1 <= input'left;
output2 <= input'right;
output3 <= input'length;
end process;
end;

First the simple answer: there is no equivalent. In Verilog
you are expected to parameterise the module and then use
those parameters to *define* port widths:

module myModule (In, Out1, Out2, Out3);
parameter left = 16, right = 1;
input [left:right] In;
output [31:0] Out1, Out2, Out3;

assign Out1 = left;
assign Out2 = right;
assign Out3 = left + 1 - right;
endmodule

Second, why do this in a module rather than inline?

Third, the future is bright: SystemVerilog will offer
built-in enquiry functions to find these array attributes.

--

Jonathan Bromley, Consultant

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