VHDL and ports

[Brad Smallridge]

Just a reality check here for a beginner.

I am under the impression, although I haven't actually seen it written, that
all IO ports have to come up through the hierarchy of entities to be
expressed at the top level. Is this true? Or can you have some IO ports
handled by lower entities, such as setting a control level to 1 or 0, and
not having the "hooks" go up to the high level?

Brad Smallridge
b r a d @ a i v i s i o n . c o m

 

[Mike Treseler]

Brad Smallridge wrote:

I am under the impression, although I haven't actually seen it written, that
all IO ports have to come up through the hierarchy of entities to be
expressed at the top level. Is this true?

Yes. One reason to minimize the number of levels.

http://groups.google.com/groups?q=my_entity+top+wiring+isaac

-- Mike Treseler