VHDL and extracing equations

[buke2]

Hello all,
anybody knows how can I extract equations from Xilinx schematic?
I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
generated...but to get clear equations (Out=f(In)) I must translate whole of
file...

Maybe somhere is tool for extracting euations from VHDL file?

Regards
Kuba

 

[Just an Illusion]

Hi Kuba,

buke2 wrote:

Hello all,
anybody knows how can I extract equations from Xilinx schematic?
I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
generated...but to get clear equations (Out=f(In)) I must translate whole of
file...


Do you need them into vhdl ? Otherwise you can perhaps use edif2blif to

generate a blif file.

Maybe somhere is tool for extracting euations from VHDL file?


The official level of input is a transistor netlist, but you can look

for TLL product from TransEDA/TNI-Valiosys
Perhaps do you have a way to keep your netlist as input.

TLL can make you a VHDL or a Verilog file with sequential process and
combinatory process.

Then you have your equations.

Regards
Kuba





Regards,

JaI

 

[buke2]

"Just an Illusion" <illusion_to_net@yahoo.fr> wrote in message
news:41079A7F.7060002@yahoo.fr...

Hi Kuba,

buke2 wrote:

Hello all,
anybody knows how can I extract equations from Xilinx schematic?
I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
generated...but to get clear equations (Out=f(In)) I must translate whole
of
file...


Do you need them into vhdl ? Otherwise you can perhaps use edif2blif to
generate a blif file.

Maybe somhere is tool for extracting euations from VHDL file?


The official level of input is a transistor netlist, but you can look
for TLL product from TransEDA/TNI-Valiosys
Perhaps do you have a way to keep your netlist as input.

TLL can make you a VHDL or a Verilog file with sequential process and
combinatory process.

Then you have your equations.

THX!!!!!!