VHDL-AMS?

[yaveh (Yet Another Vhdl E]

Any experience with the Analog and Mixed-Signal (AMS)
extensions to VHDL in this newsgroup ?

 

[Phoenix]

Dnia 24-10-2006 o 13:27:42 yaveh (Yet Another Vhdl Engineer Hoping)
<fcamarero@altek-technology.de> napisał:

Any experience with the Analog and Mixed-Signal (AMS)
extensions to VHDL in this newsgroup ?

Hi. I'm not experienced with AMS, but I'm interested this topic. If You

know about some interesting www's about AMS I will be grateful if You
place it here.

Regards
Paul

 

[bhateja.jatin@gmail.com]

On Oct 24, 11:11 pm, Phoenix
<phoeni...@wiadomo.po.co.to.jest.tenbitpl> wrote:

Dnia 24-10-2006 o 13:27:42 yaveh (Yet Another Vhdl Engineer Hoping)
fcamar...@altek-technology.de> napisał:



Any experience with the Analog and Mixed-Signal (AMS)
extensions to VHDL in this newsgroup ?Hi. I'm not experienced with AMS, but I'm interested this topic. If You
know about some interesting www's about AMS I will be grateful if You
place it here.

Regards
Paul

Hi,

Also please let me know about the synthesis tools available for analog
/ mixed signal circuits.

-- Jatin

 

[Paul Floyd]

On 24 Oct 2006 04:27:42 -0700, yaveh (Yet Another Vhdl Engineer Hoping)
<fcamarero@altek-technology.de> wrote:

Any experience with the Analog and Mixed-Signal (AMS)
extensions to VHDL in this newsgroup ?

A bit. I've just started working for Mentor Graphics on their ADVance-MS
product. If I can't answer any related questions myself, I can probably
find someone who can.

A bientot
Paul
--
Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

 

[yaveh (Yet Another Vhdl E]

Hi Paul,

I am currently not using ADVance-MS, but the other company´s
simulator, so
I think we should start with basic understanding of the language:
I have read through "The System Designer´s Guide to VHDL-AMS" from
Aschenden
and have still doubts about what the "break" statement is for, about
where analog solution points (ASP) should be computed, etc...

Maybe you can comment something on the topic?

yaveh ([..])

Paul Floyd wrote:

On 24 Oct 2006 04:27:42 -0700, yaveh (Yet Another Vhdl Engineer Hoping)
fcamarero@altek-technology.de> wrote:

Any experience with the Analog and Mixed-Signal (AMS)
extensions to VHDL in this newsgroup ?

A bit. I've just started working for Mentor Graphics on their ADVance-MS
product. If I can't answer any related questions myself, I can probably
find someone who can.

A bientot
Paul
--
Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

 

[Paul Floyd]

On 25 Oct 2006 00:44:02 -0700, yaveh (Yet Another Vhdl Engineer Hoping)
<fcamarero@altek-technology.de> wrote:

Hi Paul,

I am currently not using ADVance-MS, but the other company´s
simulator, so

Too bad. Shouldn't that be 'an' other company, though? There are at
least two others.

I think we should start with basic understanding of the language:
I have read through "The System Designer´s Guide to VHDL-AMS" from
Aschenden
and have still doubts about what the "break" statement is for, about
where analog solution points (ASP) should be computed, etc...

In the simulator, there are two kernels, analog and digital. The digital
kernel has it easy - signals have only a relative small number of
possible states, and events (changes between those states) can only
occur at discrete moments in time. The analog kernel, on the other hand,
has to deal with quantities that vary continuously. The quantities are
defined by a set of characteristic equations. These are solved using
numerical methods for differential equations. Such methods use a dynamic
time step. If the quantities change slowly, and it's easy to converge on
a solution, then the analog time step will increase. Conversely, if
there's no convergence, the analog time step will be decreased.

'break' causes the analog kernel to synchronise with the digital kernel.
This might be because there is a discontinuity in the analog quantities.

It is also possible to synchronize from the digital side, e.g., with
'above.

A bientot
Paul
--
Dr. Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

 

[yaveh (Yet Another Vhdl E]

Paul Floyd wrote:

I am currently not using ADVance-MS, but the other company´s
simulator, so

Too bad. Shouldn't that be 'an' other company, though? There are at
least two others.

Well, it actually should be "the other companies´ simulators"...

.
'break' causes the analog kernel to synchronise with the digital kernel.
This might be because there is a discontinuity in the analog quantities.
It is also possible to synchronize from the digital side, e.g., with
'above.

What do you exactly mean by "synchronise" ?

I actually expect that the analog kernel will provide an exact (within
the
tolerances) solution at the time where sampling (assignment of a
quantity
into a signal or variable) occurs.
Additionally, I expect to be able to force the analog kernel to provide
one
of the above mentioned analog solution points (or ASP) by using the
break statement in the discrete time domain, e.g.: inside a process
with e.g.:

for i in 1 to 10 loop
wait for 10 ns;
break;
end loop;

Of course, as you mentioned, you can use <quantity>´above(level) as an

implicit boolean signal that will trigger events on the discrete time
domain,
as any other signal.

What do you mean with "synchronize from the digital side" when writing
about
Q´above ?

 

[Paul Floyd]

On 26 Oct 2006 04:44:00 -0700, yaveh (Yet Another Vhdl Engineer Hoping)
<fcamarero@altek-technology.de> wrote:

Paul Floyd wrote:
I am currently not using ADVance-MS, but the other company´s
simulator, so

Too bad. Shouldn't that be 'an' other company, though? There are at
least two others.

Well, it actually should be "the other companies´ simulators"...

Even worse :-(

.
'break' causes the analog kernel to synchronise with the digital kernel.
This might be because there is a discontinuity in the analog quantities.
It is also possible to synchronize from the digital side, e.g., with
'above.

What do you exactly mean by "synchronise" ?

That analog time == digital time.

I actually expect that the analog kernel will provide an exact (within
the tolerances) solution at the time where sampling (assignment of a
quantity into a signal or variable) occurs.

I'm not sure that I fully understand yet the electrical (if any) and
temporal consequences of assigning a quantity to a variable. Conversion
between quantities and signals isn't straightforward. I'm not sure that
it causes synchronization.

Additionally, I expect to be able to force the analog kernel to provide
one of the above mentioned analog solution points (or ASP) by using the
break statement in the discrete time domain, e.g.: inside a process
with e.g.:

for i in 1 to 10 loop
wait for 10 ns;
break;
end loop;

Of course, as you mentioned, you can use <quantity>´above(level) as an
implicit boolean signal that will trigger events on the discrete time
domain, as any other signal.

What do you mean with "synchronize from the digital side" when writing
about Q´above ?

Q'above causes a digital event to occur as a result of an analog
quantity (as opposed to a break causing an analog ASP to occur at a
digital event).

A bientot
Paul
--
Dr. Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

 

[homoalteraiensis]

should it possibly be reasonable, to setup an own group here at
google's for vhdl-ams?

i am strongly interested in this nearby ...

 

[Paul Floyd]

On 7 Nov 2006 10:26:13 -0800, homoalteraiensis
<fpgaengineerfrankfurt@arcor.de> wrote:

should it possibly be reasonable, to setup an own group here at
google's for vhdl-ams?

i am strongly interested in this nearby ...

Is there enough interest? This group only gets ~10 posts a day. My guess
is that VHDL-AMS would only get ~1 a day.

Personally, I prefer real usenet newsgroups, rather than mailing lists
or proprietary 'message boards'. Still, if it's not going to be usenet,
then I'd go for a mailing list (e.g., run by mailman).

A bientot
Paul
--
Paul Floyd http://paulf.free.fr (for what it's worth)
Surgery: ennobled Gerald.

 

[Phoenix]

Dnia 07-11-2006 o 23:00:49 Paul Floyd <root@127.0.0.1> napisał:

On 7 Nov 2006 10:26:13 -0800, homoalteraiensis
fpgaengineerfrankfurt@arcor.de> wrote:

should it possibly be reasonable, to setup an own group here at
google's for vhdl-ams?

i am strongly interested in this nearby ...

Is there enough interest? This group only gets ~10 posts a day. My guess
is that VHDL-AMS would only get ~1 a day.

I agree with You. VHDL-AMS have too small interested "fans" Maybe
someday...

Regards
Phoenix

 

Also please let me know about the synthesis tools available for analog
/ mixed signal circuits.

There no viable synthesis tools for AMS circuits. Maybe having
languages like VHDL-AMS will change that, but I doubt it.