VHDL-200X-FT Packages and Xilinx XST Error

[Ivan C.]

Hi all,

I've successfully setup the floating point packages that are part
of the VHDL-200X-FT package set at:

http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html

so that I can use them under ModelSim. When trying to synthesize even
the simplest circuit using Xilinx XST (from 6.3.02i) I get the
following error:

Analyzing Entity <fp32_test> (Architecture <simple&gt.
ERROR:Xst:1548 - C:/MYModels/simple_fp_test_synthesis/simple_test.vhd
line 14: Negative range in type of signal <A> is not supported.
--&gt;

The Xilinx help page isn't very helpful other than saying that it is
correct (search for: Xilinx answer #18974)

Below is my simple_test.vhd:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% For
testing only
use ieee.math_real.all;
use work.fixed_pkg.all;
use work.fphdl_base_pkg.all;
use work.fphdl32_pkg.all;


entity fp32_test is
port( RST : in std_logic;
LINE14: A, B : in fp;
C : out fp
);
end entity fp32_test;

architecture simple of fp32_test is
begin
reset : process (RST) is
begin
if RST = '1' then
C &lt;= A + B;
end if;
end process reset;

end architecture simple;


Note that to get the packages to work I had to change the FP related
ieee.fp* to work.fp*. BTW, all the FP packages pass the XST
compilation stage.


If you need more information please let me know. I'm pretty sure
someone has run into this before and I'm doing something silly


Thanks,

Ivan C.

 

[David Bishop]

Ivan C. wrote:

When trying to synthesize even
the simplest circuit using Xilinx XST (from 6.3.02i) I get the
following error:

Analyzing Entity &lt;fp32_test&gt; (Architecture &lt;simple&gt.
ERROR:Xst:1548 - C:/MYModels/simple_fp_test_synthesis/simple_test.vhd
line 14: Negative range in type of signal <A> is not supported.
--

I already told Xilinx about this. XST can not deal with a negative
index in Synthesis.

On the other side of the coin, Synopsys (Presto compiler), Exemplar
(Leonardo Spectrum), Synplicity, Cadence buildgates, and Altera
synthesis can.

The Xilinx help page isn't very helpful other than saying that it is
correct (search for: Xilinx answer #18974)

This is typical. XST is a REALLY cheap synthesis tool. I sent this
one into them over a year ago and it still isn't fixed.

Note that to get the packages to work I had to change the FP related
ieee.fp* to work.fp*. BTW, all the FP packages pass the XST
compilation stage.


If you need more information please let me know. I'm pretty sure
someone has run into this before and I'm doing something silly

Thanks for the test. Like I said, unless we can get Xilinx off it's
duff XST is a lost cause with these packages.

 

[David Bishop]

Ivan C. wrote:

David Bishop &lt;dbishop@vhdl.org&gt; wrote in message news:&lt;DZQnd.5854$Uf.395@twister.nyroc.rr.com&gt;...

Note that to get the packages to work I had to change the FP related
ieee.fp* to work.fp*. BTW, all the FP packages pass the XST
compilation stage.

I actually wrote some quick scripts to do this for me.
Yes, since they are not in the IEEE library yet, you have to change
the reference. However, the packages will work with vhdl-93.

If you need more information please let me know. I'm pretty sure
someone has run into this before and I'm doing something silly

Thanks for the test. Like I said, unless we can get Xilinx off it's
duff XST is a lost cause with these packages.

Thanks David for the response. I'll see if we can use one of the
other tools and in parallel give the Xilinx techs another shot. Great
job putting the packages together.

Yes, the Xilinx techs on XST need to be shot.
I have fixed point math running just as fast as integer math in these
packages. I can get the floating point math to run at 80 MHz (piplined)
in a Xilinx part.

 

[Mike Treseler]

Ivan C. wrote:

so that I can use them under ModelSim. When trying to synthesize

Maybe you mean simulate

even
the simplest circuit using Xilinx XST (from 6.3.02i) I get the
following error:

Analyzing Entity &lt;fp32_test&gt; (Architecture &lt;simple&gt.
ERROR:Xst:1548 - C:/MYModels/simple_fp_test_synthesis/simple_test.vhd
line 14: Negative range in type of signal <A> is not supported.

That doesn't look like modelsim to me.

I wouldn't expect XST synthesis to work since this is
an unreleased standard.

If you wish to pursue simulation,
consider using modelsim directly and start with the
standard testbench:

http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/test_fpfixed.vhd

-- Mike Treseler

 

[Ivan C.]

David Bishop &lt;dbishop@vhdl.org&gt; wrote in message news:&lt;DZQnd.5854$Uf.395@twister.nyroc.rr.com&gt;...

Ivan C. wrote:
When trying to synthesize even
the simplest circuit using Xilinx XST (from 6.3.02i) I get the
following error:

Analyzing Entity &lt;fp32_test&gt; (Architecture &lt;simple&gt.
ERROR:Xst:1548 - C:/MYModels/simple_fp_test_synthesis/simple_test.vhd
line 14: Negative range in type of signal <A> is not supported.
--

I already told Xilinx about this. XST can not deal with a negative
index in Synthesis.

On the other side of the coin, Synopsys (Presto compiler), Exemplar
(Leonardo Spectrum), Synplicity, Cadence buildgates, and Altera
synthesis can.

The Xilinx help page isn't very helpful other than saying that it is
correct (search for: Xilinx answer #18974)

This is typical. XST is a REALLY cheap synthesis tool. I sent this
one into them over a year ago and it still isn't fixed.

Note that to get the packages to work I had to change the FP related
ieee.fp* to work.fp*. BTW, all the FP packages pass the XST
compilation stage.


If you need more information please let me know. I'm pretty sure
someone has run into this before and I'm doing something silly

Thanks for the test. Like I said, unless we can get Xilinx off it's
duff XST is a lost cause with these packages.

Thanks David for the response. I'll see if we can use one of the
other tools and in parallel give the Xilinx techs another shot. Great
job putting the packages together.


Thanks again,

Ivan