VHDL-200x fixed point package takes very long to synthesize

Hi all, I need some help, if anyone has the time to explain what I am
doing wrong

I am trying to use the fixed point package fixed_pkg and am having
trouble with synthesis

I have a process with just a few lines of code that seems to need
forever to map - it wont finish even over night on a 3Ghz machine.

I am using Synplify Pro with Xilinx ISE.

I have removed all the code lines from the process that do not seem to
make a difference with this problem.

Here is the code snippet that causes me trouble (all variables are
declared like):
shared variable m1: sfixed (32 downto -32) := to_sfixed (50, 32, -32);

process(src_clk_1)
begin
if (src_clk_1'event and src_clk_1='1') then
ykm2 := ykm1;
ykm1 := yk;
yk := to_sfixed (arg => to_integer(unsigned(val1)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
uk := to_sfixed (arg => to_integer(unsigned(val2)),
left_index => 32,
right_index => -32,
round_style => false,
overflow_style => true);
m1 := resize(ykm2*p11, m1'high,m1'low);
m2 := resize(ykm1*p21, m2'high,m2'low);
m3 := resize(uk*p31, m3'high,m3'low);
m4 := resize(m1+m2, m4'high,m4'low);
t1 := resize(m3+m4, t1'high,t1'low);
m1 := resize(t1*t1, m1'high,m1'low);
p11 := resize(p11 - m1, p11'high,p11'low);
end process;

Any insight or pointers would be appreciated


JAn

 

Hi!
Thank you for your reply.

I need to move this into hardware, so simulation is not sufficient. I
have actually had everything declared as signals and assigned the
signals in a state machine before. I felt the signals might be the
problem, so I went to the variables, but no luck.

Any other ideas?

Thanks,

JAn