VHDL 2 VERILOG CONVERTER FOR AHB

[terabits]

Hi

Any one has vhdl to verilog converter ?????
i have one but it translates only 60 lines of code.
if you have and if u cannot pass on to me, could you please conver the
ahb generator in opencores to verilog format and post it ????
as i see there are many questions about ahb models there is one is
opencores but in vhdl, conversion it to verilog would be greatly
appreciated.

Regards

 

[Utku Özcan]

"Terabits", May I ask you which HDL simulator you are using?

Utku.

terabits wrote:

Hi

Any one has vhdl to verilog converter ?????
i have one but it translates only 60 lines of code.
if you have and if u cannot pass on to me, could you please conver the
ahb generator in opencores to verilog format and post it ????
as i see there are many questions about ahb models there is one is
opencores but in vhdl, conversion it to verilog would be greatly
appreciated.

Regards

 

[terabits]

Modelsim, I know it supports mixed language simulations but i donno
VHDL

On Dec 12, 4:20 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote:

"Terabits", May I ask you which HDL simulator you are using?

Utku.

terabits wrote:
Hi

Any one has vhdl to verilog converter ?????
i have one but it translates only 60 lines of code.
if you have and if u cannot pass on to me, could you please conver the
ahb generator in opencores to verilog format and post it ????
as i see there are many questions about ahb models there is one is
opencores but in vhdl, conversion it to verilog would be greatly
appreciated.

Regards

 

[Rob Dekker]

Hi terabits,

General conversion of VHDL to Verilog or visa versa is totally non-trivial.
I doubt that there is any serious professional solution out there that can
deal with all the details of each language.

However, ModelSim supports mixed VHDL and Verilog simulation.
Also most other EDA tools support mixed language compilation,
so you would not need to translate one to the other.

Rob


"terabits" <tera.bits@gmail.com> wrote in message news:1165970270.582704.245680@16g2000cwy.googlegroups.com...
Modelsim, I know it supports mixed language simulations but i donno
VHDL

On Dec 12, 4:20 pm, "Utku Özcan" <utku.oz...@gmail.com> wrote:

"Terabits", May I ask you which HDL simulator you are using?

Utku.

terabits wrote:
Hi

Any one has vhdl to verilog converter ?????
i have one but it translates only 60 lines of code.
if you have and if u cannot pass on to me, could you please conver the
ahb generator in opencores to verilog format and post it ????
as i see there are many questions about ahb models there is one is
opencores but in vhdl, conversion it to verilog would be greatly
appreciated.

Regards

 

[Ravali Thangellapalli]

hii terabits..i have vhdl code ..can you help me to convert my code into verilog code..please help me..
thanks...