VGA display

[Abby]

Hi!
I' m working to a project a little difficult for me, 'cause for the first
time I have to simulate a chess game using Fpga and verilog language.
I need your advices!
Most of the project is realized.
Final parts concern VGA display.
I know I must work using HS and VS signals, but I don't know rightly how to
simulate all that into verilog.
I will be very happy if there's someone who can help me or suggest some
books about VGA display.
Thanx a lot! ^___^

 

[cfk]

Dear Abby:
You might find Keith Jack's book "Video Demystified" to be useful. If
you are code-centric, then find a copy of IBM's original "AT Technical
Reference Manual". Thats the 5x7 inch book in the blue cover.Barring that,
try Richard Ferraro's book "Programmers Guide to the EGA and VGA cards". And
lastly, if finding those is difficult or costly, try searching google with
some of the titles above as keywords and I suspect you will find a treasure
of information available.

Charles

"Abby" <abhigayl@hotmail.com> wrote in message
news:Tdn6b.34567$R32.1081585@news2.tin.it...

Hi!
I' m working to a project a little difficult for me, 'cause for the first
time I have to simulate a chess game using Fpga and verilog language.
I need your advices!
Most of the project is realized.
Final parts concern VGA display.
I know I must work using HS and VS signals, but I don't know rightly how
to
simulate all that into verilog.
I will be very happy if there's someone who can help me or suggest some
books about VGA display.
Thanx a lot! ^___^

 

[Abby]

"cfk" <cfk_alter_ego@pacbell.net> ha scritto nel messaggio news:L8t6b.10410


Thank you very much Charles!!!
I will try to search for some of titles you said to me.
I hope to solve my problem.

 

[jjl]

You may want to check out www.opencores.org for vga IP in verilog.

Also, a very goodprimer of vga HS/VS at:
http://www.xess.com/appnotes/vga.pdf

Finally, a non-free (for cost) comple VGA core with DMA engine and
SDRAM controller (32bit data path) in multi-clock domain at:
http://www.cmosexod.com/fnd.htm

hope this helps,


"Abby" <abhigayl@hotmail.com> wrote in message news:<pqD6b.37758$R32.1195475@news2.tin.it>...

"cfk" <cfk_alter_ego@pacbell.net> ha scritto nel messaggio news:L8t6b.10410


Thank you very much Charles!!!
I will try to search for some of titles you said to me.
I hope to solve my problem.

 

[Jan Kindt]

You also might be interested in following link :
http://home.freeuk.com/fpgaarcade/pac_main.htm

It has a very simple vga-interface implemented in VHDL. Might be
enough to kickstart your design.

 

[Jean Nicolle]

can I suggest taking a look to this tutorial?
http://www.fpga4fun.com/PongGame.html

Jean

"Abby" <abhigayl@hotmail.com> wrote in message
news:Tdn6b.34567$R32.1081585@news2.tin.it...

Hi!
I' m working to a project a little difficult for me, 'cause for the first
time I have to simulate a chess game using Fpga and verilog language.
I need your advices!
Most of the project is realized.
Final parts concern VGA display.
I know I must work using HS and VS signals, but I don't know rightly how
to
simulate all that into verilog.
I will be very happy if there's someone who can help me or suggest some
books about VGA display.
Thanx a lot! ^___^

 

[Abby]

"jjl" ha scritto nel messaggio


You may want to check out www.opencores.org for vga IP in verilog.

Also, a very goodprimer of vga HS/VS at:
http://www.xess.com/appnotes/vga.pdf

Finally, a non-free (for cost) comple VGA core with DMA engine and
SDRAM controller (32bit data path) in multi-clock domain at:
http://www.cmosexod.com/fnd.htm

hope this helps,

Second link you suggest to me is very interesting! Thanx a lot!

 

[Abby]

"Jean Nicolle" >

can I suggest taking a look to this tutorial?

http://www.fpga4fun.com/PongGame.html

Jean

Yeah, It's wonderful!!
Thx!!!
:-***

 

[Abby]

"Jan Kindt" ha scritto nel messaggio > You also might be interested in
following link :

http://home.freeuk.com/fpgaarcade/pac_main.htm

It has a very simple vga-interface implemented in VHDL. Might be
enough to kickstart your design.

Thank you very much!
I don't know VHDL language, but I think this file will be very useful when I
will start to work with VHDL too!

Thanx to all!

 

[PO Laprise]

You should be careful to try to get as close as you can to the exact timing values. We had a lab-full of students implementing VGA controllers as part of their end-of-semester project, and they managed to burn out quite a few monitors before they got the kinks worked out (luckily, they were old monitors just laying around the lab, but the lab techs still weren't too happy with them . I suggest you find up a beat-up old monitor that someone is throwing out to use for your tests... Have fun, <p>Pierre-Olivier