vga controller

for a project I need to make a vga controller.
The purpose is that their will appear 3 rectangles at the screen.
Is it possible to have a look maybe at the code,since nothing is
appearing at the screen and I have a really hard time to find the
error.

this is the timing

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vgatiming is
Port ( clock48 : in std_logic;
red : in std_logic;
blue : in std_logic;
green : in std_logic;
out_red : out std_logic;
out_blue : out std_logic;
out_green : out std_logic;
v_sync : out std_logic;
h_sync : out std_logic;
x_pointer : out std_logic_vector(9 downto 0);
y_pointer : out std_logic_vector(9 downto 0));
end vgatiming;

architecture Behavioral of vgatiming is

signal sv_sync : std_logic;
signal sh_sync : std_logic;
signal sx_pointer,sy_pointer : std_logic_vector(9 downto 0);
signal visible,vish,visv : std_logic;
signal clock24: std_logic;
begin

klokdeling: process (clock48)
--variabelen klokdelers
variable tel_klok24 : integer range 0 to 2**2-1;

--einde variabelen klokdelers

begin

if (clock48'event and clock48 = '1') then
tel_klok24 := tel_klok24 + 1;
if (tel_klok24 = 2) then
tel_klok24 := 0;
clock24 <= '1';


else
clock24 <= '0';
end if;
end if;

end process klokdeling;

timing: process (clock24)
begin



if (clock24'EVENT) and (clock24='1')then

-- generatie horizontale timing
-- Horiz_sync ------------------------------------__________--------

-- H_count 0 640 659 755 799


if (sx_pointer = 799)then


sx_pointer <= "0000000000";

else

sx_pointer <= sx_pointer + 1;

end if;

-- generatie horizontale signaal

if (sx_pointer <= 755) and (sx_pointer >= 659) then

sh_sync <= '0';

else

sh_sync <= '1';

end if;

-- generatie verticale timing
-- Vert_sync
-----------------------------------------------_______------------

-- V_count 0 480
493-494 524



if (sy_pointer = 524) and (sx_pointer >= 699) then


sy_pointer <= "0000000000";

else

sy_pointer <= sy_pointer + 1;

end if;

-- generatie vericaal signaal

if (sy_pointer <= 494) and (sx_pointer >= 493) then

sh_sync <= '0';

else

sh_sync <= '1';

end if;


-- generatie visible signaal

if (sx_pointer <= 639) then

vish <= '1';

x_pointer <= sx_pointer;

else

vish <= '0';

end if;


if (sy_pointer <= 479) then

visv <= '1';

y_pointer <= sy_pointer;

else

visv <= '0';

end if;


end if;

-- signalen uitsturen op uitgangen
out_red <= red and visible;
out_green <= green and visible;
out_blue <= blue and visible;
h_sync <= sh_sync;
v_sync <= sv_sync;



end process timing;

-- totale visible signaal = wanneer visv en vish hoog zijn

visible <= vish and visv;


end Behavioral;


this is the top program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;


-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vgatest is
port(clock48 : in std_logic;
R, G, B, H, V : out std_logic ;
ramre : out std_logic;
ramwe : out std_logic;
flashre : out std_logic;
flashwe : out std_logic);

end vgatest;

architecture Behavioral of vgatest is



component vgatiming is

Port ( clock48 : in std_logic;
red : in std_logic;
blue : in std_logic;
green : in std_logic;
out_red : out std_logic;
out_blue : out std_logic;
out_green : out std_logic;
v_sync : out std_logic;
h_sync : out std_logic;
x_pointer : out std_logic_vector(9 downto 0);
y_pointer : out std_logic_vector(9 downto 0));
end component;




signal row, column : std_logic_vector(9 downto 0);
signal red, green, blue : std_logic;
--signal clock_24 : std_logic;

begin

ramre <= '1';
ramwe <= '1';
flashre <= '1';
flashwe <= '1';





-- for debugging: to view the bit order
timing : component vgatiming
port map ( clock48 => clock48, red => red, green => green, blue =>
blue,
y_pointer => row, x_pointer=> column,
out_red => R, out_green => G, out_blue => B, h_sync =>
H, v_sync => V);






-- red square from 0,0 to 360, 350
-- green square from 0,250 to 360, 640
-- blue square from 120,150 to 480,500




RGB : process(row, column)
begin
-- wait until clock = '1';

if row < 360 and column < 350 then
red <= '1';
else
red <= '0';
end if;

if row < 360 and column > 250 and column < 640 then
green <= '1';
else
green <= '0';
end if;

if row > 120 and row < 480 and column > 150 and column < 500 then
blue <= '1';
else
blue <= '0';
end if;

end process;



end Behavioral;





thanks for having a look at it!!
kind regards

 

the screen is staying in power save mode.So I guess it is confused by
the syncing.
The timing is calculated for a 800 *524 display(640 ,480).

And the RBG signals are departing from the board.but they have to,
right?
I don 't know what you mean by this?
the R,B,G an hor,ver sync have to be connected to the board.

 

I've tried what you said,but the screen is staying in powersave mode.
Somebody in school told me that it is possible to send the logic signal
straight to the screen.
Thanks for your help!!

 

it's working!!!

 

this is the working code,I just have to make small adjustments to the
clock



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity vgatiming is
Port ( clock48 : in std_logic;
red : in std_logic;
blue : in std_logic;
green : in std_logic;
out_red : out std_logic;
out_blue : out std_logic;
out_green : out std_logic;
v_sync : out std_logic;
h_sync : out std_logic;
x_pointer : out std_logic_vector(9 downto 0);
y_pointer : out std_logic_vector(9 downto 0));
end vgatiming;

architecture Behavioral of vgatiming is

signal sv_sync : std_logic;
signal sh_sync : std_logic;
signal sx_pointer,sy_pointer : std_logic_vector(9 downto 0);
signal visible,vish,visv : std_logic;
signal clock24: std_logic;
begin

klokdeling: process (clock48)
--variabelen klokdelers
variable tel_klok24 : integer range 0 to 2**2-1;

--einde variabelen klokdelers

begin

x_pointer <= sx_pointer;
y_pointer <= sy_pointer;


if (clock48'event and clock48 = '1') then
tel_klok24 := tel_klok24 + 1;
if (tel_klok24 = 2) then
tel_klok24 := 0;
clock24 <= '1';


else
clock24 <= '0';
end if;
end if;

end process klokdeling;

timing: process (clock24)
begin



if (clock24'EVENT) and (clock24='1')then

-- generatie horizontale timing
-- Horiz_sync ------------------------------------__________--------

-- H_count 0 640 659 755 799


if (sx_pointer = 799)then


sx_pointer <= "0000000000";

else

sx_pointer <= sx_pointer + 1;

end if;

-- generatie horizontale signaal

if (sx_pointer <= 755) and (sx_pointer >= 659) then

sh_sync <= '0';

else

sh_sync <= '1';

end if;

-- generatie verticale timing
-- Vert_sync
-----------------------------------------------_______------------

-- V_count 0 480
493-494 524


if (sx_pointer=799) then
if (sy_pointer = 524) then
sy_pointer <= "0000000000";
else
sy_pointer <= sy_pointer + 1;
end if;
end if;

-- generatie vericaal signaal

if (sy_pointer <= 494) and (sy_pointer >= 492) then
sv_sync <= '0';
else
sv_sync <= '1';
end if;


-- generatie visible signaal

if (sx_pointer <= 639) then

vish <= '1';



else

vish <= '0';

end if;


if (sy_pointer <= 479) then

visv <= '1';


else

visv <= '0';

end if;


end if;

-- signalen uitsturen op uitgangen
out_red <= red and visible;
out_green <= green and visible;
out_blue <= blue and visible;
h_sync <= sh_sync;
v_sync <= sv_sync;



end process timing;

-- totale visible signaal = wanneer visv en vish hoog zijn

visible <= vish and visv;


end Behavioral;

 

[Mich]

Hi
I have the same assignment as JO
Also I have some troubles whit the timing
can some have a look at my code?

thanks
Mich


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity
entity timingscherm is
Port ( klok48 : in std_logic;
klok_HS : out std_logic;
klok_VS : out std_logic;
zichtbaar : out std_logic;
xp : out std_logic_vector (9 downto 0);
yp : out std_logic_vector (8 downto 0)
);
end timingscherm;
--end entity

--architecture
architecture Behavioral of timingscherm is

--signalen maken
signal zichtx : std_logic;
signal zichty : std_logic;
signal klok_24 : std_logic;
--eind signalen

begin

--klok_HS <= '0';
--klok_VS <= '0';
--zichtbaar <= '0';
--xp <= "0000000000";
--yp <= "000000000";

--zichtx <= '0';
--zichty <= '0';


klokdeling: process (klok48)
--variabelen klokdelers
variable tel_HS : integer range 0 to 1599;
variable tel_VS : integer range 0 to 524;
variable tel_x : integer range 0 to 639;
variable tel_y : integer range 0 to 479;
variable tel_24 : integer range 0 to 2;
--einde variabelen klokdelers

begin
if (klok48'event and klok48 = '1') then --if voor klokdeler
--klok 24 WERKT
tel_24 := tel_24 + 1;
if (tel_24 = 2) then
tel_24 := 0;
klok_24 <= '1';
else
klok_24 <= '0';
end if;
--einde klok 24

tel_HS := tel_HS + 1;
if (tel_HS = 1599) then --klok HS
tel_HS := 0;
klok_HS <= '0';

--kijken naar VS
tel_VS := tel_VS + 1;
if (tel_VS = 524) then --klok VS
tel_VS := 0;
klok_VS <= '0';
else
if (tel_VS = 4) then
klok_VS <= '1';
end if;
if (tel_VS > 44 and tel_VS < 520) then
zichty <= '1';
tel_y := tel_y + 1;
else
zichty <= '0';
tel_y := 0;
end if;
end if;
else
if (tel_HS = 192) then
klok_HS <= '1';
end if;
if (tel_HS > 240 and tel_HS < 1520) then
zichtx <= '1';
if (klok_24 = '1') then
tel_x := tel_x +1;
end if;
else
zichtx <= '0';
tel_x := 0;
end if;
end if;

zichtbaar <= zichtx and zichty ='1'

end if;

xp <= CONV_STD_LOGIC_VECTOR (tel_x, 10);
yp <= CONV_STD_LOGIC_VECTOR (tel_y, 9);

end process klokdeling;

end Behavioral;
--end architecture