vertical capacitors

[S. Badel]

are there functions to extract vertical capacitors from a layout?
by vertical, i mean the capacitor would be formed not
by two conductive planes on two different layers,
but rather between two metal lines on the same layer,
(ie exploiting fringing capacitance between two lines)
eventually repeating this structure on multiple layers.

right now we are using calibre, but moving to another
tool could be considered.

stephane

 

[Bernd Fischer]

Hi,

You should be able to do a parasitic C extraction on
such structures.

We recently measured such a vertical finger cap test structure
and the parasitic extraction was close to measured value.

See,
http://groups.google.de/groups?selm=3D3FB4C2.A6739FB%40xignal.de&output=gplain
but I got nor reply on this.

Maybe this helps you.

Bernd

S. Badel wrote:

are there functions to extract vertical capacitors from a layout?
by vertical, i mean the capacitor would be formed not
by two conductive planes on two different layers,
but rather between two metal lines on the same layer,
(ie exploiting fringing capacitance between two lines)
eventually repeating this structure on multiple layers.

right now we are using calibre, but moving to another
tool could be considered.

stephane

 

[S. Badel]

thanks for your reply bernd.
but i did not fully understand the type of structure
you made.

what i'd want is this :

top view :
+--+ +--+
| | | |
------| | | |------
------| | | |------
| | | |
+--+ +--+

side view :

+--+ +--+
| | | | MET3
+--+ +--+
|| || VIA2
+--+ +--+
| | | | MET2
+--+ +--+
|| || VIA
+--+ +--+
====| | | |==== MET1
+--+ +--+

for example.
anyway i'll look at your script, thanks!
stephane


"Bernd Fischer" <bernd.fischer@xignal.de> wrote in message news:3FA2376C.8000703@xignal.de...

Hi,

You should be able to do a parasitic C extraction on
such structures.

We recently measured such a vertical finger cap test structure
and the parasitic extraction was close to measured value.

See,
http://groups.google.de/groups?selm=3D3FB4C2.A6739FB%40xignal.de&output=gplain
but I got nor reply on this.

Maybe this helps you.

Bernd

S. Badel wrote:
are there functions to extract vertical capacitors from a layout?
by vertical, i mean the capacitor would be formed not
by two conductive planes on two different layers,
but rather between two metal lines on the same layer,
(ie exploiting fringing capacitance between two lines)
eventually repeating this structure on multiple layers.

right now we are using calibre, but moving to another
tool could be considered.

stephane