P
Paul Hartke
Guest
Verilog's inventor nabs EDA's Kaufman award
Richard Goering
(11/07/2005 10:00 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=173402596
Santa Cruz, Calif. - It was a casual suggestion on his first day at a
new job that led Phil Moorby to invent the Verilog language and
Verilog-XL simulator. In so doing, he helped build the foundation of
modern IC design - and last week Moorby received the EDA industry's
highest accolade for that innovati on.
The EDA Consortium presented Moorby with its annual Phil Kaufman award,
which honors individuals who have made key contributions to electronic
design automation.
Given the widespread use of Verilog for both simulation and synthesis,
it would be hard to find someone who has had a greater impact. Yet, the
inventor of the Verilog language is a soft-spoken, behind-the-scenes guy
who has been content to work on hardware description languages (HDLs)
and simulation for nearly 30 years. In fact, Moorby is still at it, as a
Synopsys Inc. scientist
working on SystemVerilog and the VCS Verilog simulator.
The Verilog language was a turning point for chip design. Despite some
initial resistance, it led the move from gate-level schematic capture to
text-based entry. It also paved the way to the RTL simulation and
synthesis technologies that are universally used for chip design today.
And it survived a challenge from VHDL, which nearly all EDA vendors and
observers thought would replace Verilog more than a decade ago.
'Interesting combination'
Moorby got his start in EDA long before the term existed. In the 1970s,
he did a master's project at Manchester University in England on test
generation for printed-circuit boards. "It was an interesting
combination of hardware and software, and the advice I got was that it
was difficult to do both," he recalled. "I liked it enough that I wanted
to continue more or less in the same field."
In 1976, Moorby went to Brunel University in England to pursue a PhD
research program on dynamic timing analysis. But he soon became involved
in a project centered on one of the very first HDLs: Hilo. One reason:
The Hilo project was funded, allowing Moorby to draw a salary. The Hilo
language and simulator were subsequently sold by Genrad well into the
1980s.
Moorby was so consumed by the Hilo project that he never finished his
PhD.
"I've always wondered if not getting a PhD in my 20s would ever hinder
my career, but now, receiving the Phil Kaufman award in my 50s, I think
my concern has somewhat dissipated," he said.
One of the early customers of Hilo was Prabhu Goel, founder of Gateway
Design Automation. In 1983, Moorby moved to the United States to join
Gateway, which at that time had a test-generation product and was
seeking to develop a synthesis product based on the research of Chi-Lai
Huang, who had recently joined the company.
"The day I joined Gateway, I convinced Prabhu that the synthesis product
would need a new language and simulator to go with it, and so the
Verilog HDL and simulator were born," Moorby said. He and Huang put
together the Verilog spec in about a month. Moorby then wrote the
Verilog language, parser and simulator by himself in one year.
"When you're on your own and you've got a vision of the goal, you just
go for it," Moorby said. "In my experience, you'll always make a project
as large as the money you have."
When Verilog first came out, Moorby recalled, many older engineers liked
the demo but wondered where the graphical interface was. There wasn't
much interest in register-transfer-level design at first. But some of
the younger engineers warmed to text-based entry and started to look at
RTL, he said.
What customers really wanted was a fast gate-level simulator, and at
this point, Gateway didn't have one. So Moorby went back to the drawing
board and invented the Verilog-XL simulator, which came into widespread
use in the late 1980s, becoming the "golden" simulator for most ASIC
vendors.
In the late 1980s, said Moorby, came a "double hit" that really put
Verilog on the map. The first was the broad acceptance of Verilog-XL.
The second was the emergence of Synopsys and its Design Compiler
product, which pioneered RTL synthesis using Verilog.
Another transition was also under way, Moorby noted. Until the
mid-1980s, HDLs had been oriented to the test market; Moorby, in fact,
developed a fault simulator to go along with Verilog. Following the
introduction of Verilog-XL, the market began to be driven by
verification rather than test.
When Cadence Design Systems Inc. bought Gateway in 1990, Moorby joined
Cadence and continued working on Verilog simulation. Cadence decided to
open Verilog for standardization. But by now, most other EDA vendors
were pushing VHDL as an industry standard and a Verilog replacement.
Moorby himself ended up working on VHDL at Cadence. "Outside of our own
customer base, it was almost politically incorrect to talk about
Verilog," Moorby said. "People thought VHDL would take over the world.
We weren't sure; we had a lot of customers who said they weren't going
to give up Verilog."
And that's what happened. A groundswell of support by chip designers
kept the language alive, especially in the United States, where it
remains the dominant HDL. While many simulators today support both
languages, most chip design is done in Verilog.
Moorby left Cadence in 1992 and quit EDA for several years. Among other
things, he worked for a video company writing software that could
extract camera path and depth information from a video sequence. But he
was also on the technical board of startup Co-Design Automation, and he
joined that company in 1998, following Co-Design's development of the
Superlog language.
Superlog roots
After Synopsys acquired Co-Design in 2001, Superlog became the basis of
SystemVerilog - the biggest enhancement of Verilog since its inception.
SystemVerilog adds support for assertions and testbench generation,
making Verilog a hardware verification language as well as an HDL.
Despite having made a lot of the right calls in the past, Moorby is
hesitant to predict the future of HDLs. "Innovation is always a
surprise," he said. "If we can predict future trends, then it would not
be a surprise and, by definition, would not be innovation." But he does
believe that SystemVerilog has a strong future. "It has become so much
more than just an HDL, and the tools have already proven themselves," he
said.
Looking ahead, Moorby sees two avenues of growth for EDA. One is formal
tools, which he thinks will come on slowly but are "absolutely
necessary." What may be more exciting, he said, is a new breed of
software tools that can support multiprocessing, automatically
distributing tasks over parallel processors and communications devices.
"Companies like Intel can't make a single CPU go much faster, so they're
putting multiple cores on chips," he said. "I think that spells a
fundamental shift. We have to continue to think of ways to take
advantage of the hardware that's being built."
Richard Goering
(11/07/2005 10:00 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=173402596
Santa Cruz, Calif. - It was a casual suggestion on his first day at a
new job that led Phil Moorby to invent the Verilog language and
Verilog-XL simulator. In so doing, he helped build the foundation of
modern IC design - and last week Moorby received the EDA industry's
highest accolade for that innovati on.
The EDA Consortium presented Moorby with its annual Phil Kaufman award,
which honors individuals who have made key contributions to electronic
design automation.
Given the widespread use of Verilog for both simulation and synthesis,
it would be hard to find someone who has had a greater impact. Yet, the
inventor of the Verilog language is a soft-spoken, behind-the-scenes guy
who has been content to work on hardware description languages (HDLs)
and simulation for nearly 30 years. In fact, Moorby is still at it, as a
Synopsys Inc. scientist
working on SystemVerilog and the VCS Verilog simulator.
The Verilog language was a turning point for chip design. Despite some
initial resistance, it led the move from gate-level schematic capture to
text-based entry. It also paved the way to the RTL simulation and
synthesis technologies that are universally used for chip design today.
And it survived a challenge from VHDL, which nearly all EDA vendors and
observers thought would replace Verilog more than a decade ago.
'Interesting combination'
Moorby got his start in EDA long before the term existed. In the 1970s,
he did a master's project at Manchester University in England on test
generation for printed-circuit boards. "It was an interesting
combination of hardware and software, and the advice I got was that it
was difficult to do both," he recalled. "I liked it enough that I wanted
to continue more or less in the same field."
In 1976, Moorby went to Brunel University in England to pursue a PhD
research program on dynamic timing analysis. But he soon became involved
in a project centered on one of the very first HDLs: Hilo. One reason:
The Hilo project was funded, allowing Moorby to draw a salary. The Hilo
language and simulator were subsequently sold by Genrad well into the
1980s.
Moorby was so consumed by the Hilo project that he never finished his
PhD.
"I've always wondered if not getting a PhD in my 20s would ever hinder
my career, but now, receiving the Phil Kaufman award in my 50s, I think
my concern has somewhat dissipated," he said.
One of the early customers of Hilo was Prabhu Goel, founder of Gateway
Design Automation. In 1983, Moorby moved to the United States to join
Gateway, which at that time had a test-generation product and was
seeking to develop a synthesis product based on the research of Chi-Lai
Huang, who had recently joined the company.
"The day I joined Gateway, I convinced Prabhu that the synthesis product
would need a new language and simulator to go with it, and so the
Verilog HDL and simulator were born," Moorby said. He and Huang put
together the Verilog spec in about a month. Moorby then wrote the
Verilog language, parser and simulator by himself in one year.
"When you're on your own and you've got a vision of the goal, you just
go for it," Moorby said. "In my experience, you'll always make a project
as large as the money you have."
When Verilog first came out, Moorby recalled, many older engineers liked
the demo but wondered where the graphical interface was. There wasn't
much interest in register-transfer-level design at first. But some of
the younger engineers warmed to text-based entry and started to look at
RTL, he said.
What customers really wanted was a fast gate-level simulator, and at
this point, Gateway didn't have one. So Moorby went back to the drawing
board and invented the Verilog-XL simulator, which came into widespread
use in the late 1980s, becoming the "golden" simulator for most ASIC
vendors.
In the late 1980s, said Moorby, came a "double hit" that really put
Verilog on the map. The first was the broad acceptance of Verilog-XL.
The second was the emergence of Synopsys and its Design Compiler
product, which pioneered RTL synthesis using Verilog.
Another transition was also under way, Moorby noted. Until the
mid-1980s, HDLs had been oriented to the test market; Moorby, in fact,
developed a fault simulator to go along with Verilog. Following the
introduction of Verilog-XL, the market began to be driven by
verification rather than test.
When Cadence Design Systems Inc. bought Gateway in 1990, Moorby joined
Cadence and continued working on Verilog simulation. Cadence decided to
open Verilog for standardization. But by now, most other EDA vendors
were pushing VHDL as an industry standard and a Verilog replacement.
Moorby himself ended up working on VHDL at Cadence. "Outside of our own
customer base, it was almost politically incorrect to talk about
Verilog," Moorby said. "People thought VHDL would take over the world.
We weren't sure; we had a lot of customers who said they weren't going
to give up Verilog."
And that's what happened. A groundswell of support by chip designers
kept the language alive, especially in the United States, where it
remains the dominant HDL. While many simulators today support both
languages, most chip design is done in Verilog.
Moorby left Cadence in 1992 and quit EDA for several years. Among other
things, he worked for a video company writing software that could
extract camera path and depth information from a video sequence. But he
was also on the technical board of startup Co-Design Automation, and he
joined that company in 1998, following Co-Design's development of the
Superlog language.
Superlog roots
After Synopsys acquired Co-Design in 2001, Superlog became the basis of
SystemVerilog - the biggest enhancement of Verilog since its inception.
SystemVerilog adds support for assertions and testbench generation,
making Verilog a hardware verification language as well as an HDL.
Despite having made a lot of the right calls in the past, Moorby is
hesitant to predict the future of HDLs. "Innovation is always a
surprise," he said. "If we can predict future trends, then it would not
be a surprise and, by definition, would not be innovation." But he does
believe that SystemVerilog has a strong future. "It has become so much
more than just an HDL, and the tools have already proven themselves," he
said.
Looking ahead, Moorby sees two avenues of growth for EDA. One is formal
tools, which he thinks will come on slowly but are "absolutely
necessary." What may be more exciting, he said, is a new breed of
software tools that can support multiprocessing, automatically
distributing tasks over parallel processors and communications devices.
"Companies like Intel can't make a single CPU go much faster, so they're
putting multiple cores on chips," he said. "I think that spells a
fundamental shift. We have to continue to think of ways to take
advantage of the hardware that's being built."