VerilogIn does nothing...

[NigelD]

Hi,

I have a synthesized verilog netlist (created using Synopys Design
Compiler) that I would like to bring in to cadence so I can do place
and route. However, whenever I try to use it, it does nothing at all.
It claims to start and finish, but when I look at the log file, it just
says "End of logfile" and there is no schematic created in the target
library. I have even paired down the verilog to have only a single OR
gate within the module description and I get the same results. The
reference library does exist and only cells from the reference library
are used.

Does anyone have *any* suggestions at all? I'm getting very frustrated
with no information at all in the log files...

Thanks in advance!

nigel.

 

[Andrew Beckett]

On 4 Aug 2006 10:02:00 -0700, "NigelD" <ndrego@gmail.com> wrote:

Hi,

I have a synthesized verilog netlist (created using Synopys Design
Compiler) that I would like to bring in to cadence so I can do place
and route. However, whenever I try to use it, it does nothing at all.
It claims to start and finish, but when I look at the log file, it just
says "End of logfile" and there is no schematic created in the target
library. I have even paired down the verilog to have only a single OR
gate within the module description and I get the same results. The
reference library does exist and only cells from the reference library
are used.

Does anyone have *any* suggestions at all? I'm getting very frustrated
with no information at all in the log files...

Thanks in advance!

nigel.

We had an issue reported the other day where somebody was tryng to do this with
a protected netlist - in fact it was encrypted using some non-Cadence tool.

As a result, the contents where not visible, and so it didn't see any modules in
the file, and so thought it had imported everything!

The same thing happens if you use ncprotect to protect a whole file - because
the module names and I/Os are not visible, you can't import it (even as a
textual view) because it needs to know what cell name to store it under - and
this is not visible within the file.

Perhaps this is the reason? It's not a bug if this is the problem - that's the
way it has to be for protection of the verilog to make any sense.

Andrew.
--
Andrew Beckett
Principal European Technology Leader
Cadence Design Systems, UK.