verilogger

[}{]

I am having a little trouble with an and gate in verilogger, I have 5
registers that can change state on the rising edge of a clock pulse, when I
do this,

and(val_out, reg1, reg2, reg3, reg4, reg5);

everything seems fine, ie val_out = 1 when all of the registers = 1;

If however, I add a simple 1 to the end eg

and(val_out, reg1, reg2, reg3, reg4, reg5, 1);

when all of the regs are 1, val_out is unknown.

This may seem like a silly thing to do anyway but I discovered it while
trying to do something else.


As mentioned, the registers are checked on the rising edge of the clock
pulse, if val_out equates to a 1, it stays that way until the next rising
edge. Ideally, I would like it to fall to zero again at the falling edge of
the clock. I thought the simplest way to do this would be to add another
register that is set to 0 on the falling edge of the clock and include it in
the and logic. I got the problems described above, that is when I thought
about just making it a constant 1, to try to work out where I was going
wrong.

I am a total newbie so please be gentle, but any pointers would be
appreciated.

Thanks

 

[Rajkumar]

On Jul 5, 12:04 am, "}{" <snoozegro...@blueyonder.co.uk> wrote:

I am having a little trouble with an and gate in verilogger, I have 5
registers that can change state on the rising edge of a clock pulse, when I
do this,

and(val_out, reg1, reg2, reg3, reg4, reg5);

everything seems fine, ie val_out = 1 when all of the registers = 1;

If however, I add a simple 1 to the end eg

and(val_out, reg1, reg2, reg3, reg4, reg5, 1);

when all of the regs are 1, val_out is unknown.

This may seem like a silly thing to do anyway but I discovered it while
trying to do something else.

As mentioned, the registers are checked on the rising edge of the clock
pulse, if val_out equates to a 1, it stays that way until the next rising
edge. Ideally, I would like it to fall to zero again at the falling edge of
the clock. I thought the simplest way to do this would be to add another
register that is set to 0 on the falling edge of the clock and include it in
the and logic. I got the problems described above, that is when I thought
about just making it a constant 1, to try to work out where I was going
wrong.

I am a total newbie so please be gentle, but any pointers would be
appreciated.

Thanks

HI ,
Please attach the code.

Rajkumar...

 

[gabor]

On Jul 4, 3:04 pm, "}{" <snoozegro...@blueyonder.co.uk> wrote:

I am having a little trouble with an and gate in verilogger, I have 5
registers that can change state on the rising edge of a clock pulse, when I
do this,

and(val_out, reg1, reg2, reg3, reg4, reg5);

everything seems fine, ie val_out = 1 when all of the registers = 1;

If however, I add a simple 1 to the end eg

and(val_out, reg1, reg2, reg3, reg4, reg5, 1);

when all of the regs are 1, val_out is unknown.

This may seem like a silly thing to do anyway but I discovered it while
trying to do something else.

As mentioned, the registers are checked on the rising edge of the clock
pulse, if val_out equates to a 1, it stays that way until the next rising
edge. Ideally, I would like it to fall to zero again at the falling edge of
the clock. I thought the simplest way to do this would be to add another
register that is set to 0 on the falling edge of the clock and include it in
the and logic. I got the problems described above, that is when I thought
about just making it a constant 1, to try to work out where I was going
wrong.

I am a total newbie so please be gentle, but any pointers would be
appreciated.

Thanks

It may work better with 1'b1 instead of just 1. Without any size
information
the constant 1 defaults to a 32-bit integer.