VerilogAMS Config View problem

D

Debjit

Guest
Dear All,

I have written the following codes in verilogAMS . This is a TestBench
which will drive a regulator (whose code is also given ) .
I want to simulate the regulator along with the following testbench in
AMS simulator using NCSim. For that I created config view using the
AMS template. But in the config view the instantiated Resistor,
Capacitor are shown in red color. I am unable to fix the problem. I am
using the default Start and Stop view list.

Please help.

My tool versions are as follows:

ICFB Version: sub-version 5.10.41.500.6.141
Spectre Version: sub-version 7.2.0.202.isr5
NCSim Version: 08.20-s023
/////////////////////Test Bench Code////////////////////////////
`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module testbench_regulator;

electrical in, out, probe_in;
parameter Vin=5.0;
wire switch;
logic switch;
reg clk, clk_0, clk_1, enable;
logic clk, clk_0, clk_1, enable;
real check=0.0;

integer testInt = 5;

regulator regulator1(in,out,switch,probe_in,enable);

always #10 clk=~clk;
always #7 clk_0=~clk_0;
always #13 clk_1=~clk_1;

always@(posedge clk)
begin
check=V(in)-V(out);
end

initial begin
$dumpvars();
$dumpfile("digitalSignal.vcd");
clk=0;
clk_0=0;
clk_1=1;
enable =0;
#500 enable = 1;
#10000 enable = 0;
#5000 enable = 1;
#10000 enable = 0;
#5000 enable = 1;
#10000 $finish;
end

analog begin
V(in) <+ Vin;
end

endmodule
/////////////////////////////// Test Bench
Code /////////////////////////////////////


/////////////////////////////// Regulator
Code /////////////////////////////////////////

`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module regulator(in,out,switch,probe_in,enable);

parameter real C=10n;
parameter real L=10u;
parameter real R=100;
parameter tolerance=0.01;


output switch;
logic switch;
input in;
output out, probe_in;
electrical in, out, agnd, probe_in;
ground agnd;
reg switch;
input enable;
logic enable;
real vinvalue;

electrical p,q;

inductor #(.l(L)) l1(p,q);
capacitor #(.c(C)) c1(q,agnd);
resistor #(.r(R)) r1(q,agnd);

initial begin
switch = 0;
end

always@(cross(V(q)-3.0-tolerance,+1)) switch=1;
always@(cross(V(q)-3.0+tolerance,-1)) switch=0;

analog begin

@(cross(V(q)-3.0-tolerance,+1));
@(cross(V(q)-3.0+tolerance,-1));

if(enable) begin
vinvalue = V(in);
if(switch==0) begin
V(p) <+ vinvalue;
end
else if(switch==1) begin
V(p) <+ 0;
end
else begin
V(p) <+ vinvalue;
end
end
else begin
vinvalue = 0;
end

V(out) <+ V(q);
V(probe_in) <+ V(p);
end

endmodule

/////////////////////////////////////////// Regulator
Code .///////////////////////////////////

Thanks in advance for your support and help.

Thanks and Regards !!!!

Cheers !!!!!

Debjit.
 
On May 11, 8:26 pm, Debjit <debjit...@gmail.com> wrote:
Dear All,

I have written the following codes in verilogAMS . This is a TestBench
which will drive a regulator (whose code is also given ) .
I want to simulate the regulator along with the following testbench in
AMS simulator using NCSim. For that I created config view using the
AMS template. But in the config view the instantiated Resistor,
Capacitor are shown in red color. I am unable to fix the problem. I am
using the default Start and Stop view list.

Please help.

My tool versions are as follows:

ICFB Version:  sub-version 5.10.41.500.6.141
Spectre Version:  sub-version  7.2.0.202.isr5
NCSim Version:  08.20-s023
/////////////////////Test Bench Code////////////////////////////
`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module testbench_regulator;

electrical in, out, probe_in;
parameter Vin=5.0;
wire switch;
logic switch;
reg clk, clk_0, clk_1, enable;
logic clk, clk_0, clk_1, enable;
real check=0.0;

integer testInt = 5;

regulator regulator1(in,out,switch,probe_in,enable);

always #10 clk=~clk;
always #7 clk_0=~clk_0;
always #13 clk_1=~clk_1;

always@(posedge clk)
begin
        check=V(in)-V(out);
end

initial begin
        $dumpvars();
        $dumpfile("digitalSignal.vcd");
        clk=0;
        clk_0=0;
        clk_1=1;
        enable =0;
        #500 enable = 1;
        #10000 enable = 0;
        #5000 enable = 1;
        #10000 enable = 0;
        #5000 enable = 1;
        #10000 $finish;
end

analog begin
        V(in) <+ Vin;
end

endmodule
/////////////////////////////// Test Bench
Code /////////////////////////////////////

/////////////////////////////// Regulator
Code /////////////////////////////////////////

`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module regulator(in,out,switch,probe_in,enable);

parameter real C=10n;
parameter real L=10u;
parameter real R=100;
parameter tolerance=0.01;

output switch;
logic switch;
input in;
output out, probe_in;
electrical in, out, agnd, probe_in;
ground agnd;
reg switch;
input enable;
logic enable;
real vinvalue;

electrical p,q;

inductor #(.l(L)) l1(p,q);
capacitor #(.c(C)) c1(q,agnd);
resistor #(.r(R)) r1(q,agnd);

initial begin
        switch = 0;
end

always@(cross(V(q)-3.0-tolerance,+1)) switch=1;
always@(cross(V(q)-3.0+tolerance,-1)) switch=0;

analog begin

        @(cross(V(q)-3.0-tolerance,+1));
        @(cross(V(q)-3.0+tolerance,-1));

        if(enable) begin
                vinvalue = V(in);
                if(switch==0) begin
                        V(p) <+ vinvalue;
                end
                else if(switch==1) begin
                        V(p) <+ 0;
                end
                else begin
                        V(p) <+ vinvalue;
                end
        end
        else begin
                vinvalue = 0;
        end

        V(out) <+ V(q);
        V(probe_in) <+ V(p);
end

endmodule

/////////////////////////////////////////// Regulator
Code .///////////////////////////////////

Thanks in advance for your support and help.

Thanks and Regards !!!!

Cheers !!!!!

Debjit.
Click to expand...
Dear All,

Can any one help me on this?

Early help is solicited.

Thanks and Regards !!!

Debjit.
 
Debjit wrote, on 05/14/10 05:03:
On May 11, 8:26 pm, Debjit<debjit...@gmail.com> wrote:
Dear All,

I have written the following codes in verilogAMS . This is a TestBench
which will drive a regulator (whose code is also given ) .
I want to simulate the regulator along with the following testbench in
AMS simulator using NCSim. For that I created config view using the
AMS template. But in the config view the instantiated Resistor,
Capacitor are shown in red color. I am unable to fix the problem. I am
using the default Start and Stop view list.

Please help.

My tool versions are as follows:

ICFB Version: sub-version 5.10.41.500.6.141
Spectre Version: sub-version 7.2.0.202.isr5
NCSim Version: 08.20-s023
/////////////////////Test Bench Code////////////////////////////
`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module testbench_regulator;

electrical in, out, probe_in;
parameter Vin=5.0;
wire switch;
logic switch;
reg clk, clk_0, clk_1, enable;
logic clk, clk_0, clk_1, enable;
real check=0.0;

integer testInt = 5;

regulator regulator1(in,out,switch,probe_in,enable);

always #10 clk=~clk;
always #7 clk_0=~clk_0;
always #13 clk_1=~clk_1;

always@(posedge clk)
begin
check=V(in)-V(out);
end

initial begin
$dumpvars();
$dumpfile("digitalSignal.vcd");
clk=0;
clk_0=0;
clk_1=1;
enable =0;
#500 enable = 1;
#10000 enable = 0;
#5000 enable = 1;
#10000 enable = 0;
#5000 enable = 1;
#10000 $finish;
end

analog begin
V(in)<+ Vin;
end

endmodule
/////////////////////////////// Test Bench
Code /////////////////////////////////////

/////////////////////////////// Regulator
Code /////////////////////////////////////////

`timescale 1ns/10ps
`include "disciplines.vams"
`include "constants.vams"

module regulator(in,out,switch,probe_in,enable);

parameter real C=10n;
parameter real L=10u;
parameter real R=100;
parameter tolerance=0.01;

output switch;
logic switch;
input in;
output out, probe_in;
electrical in, out, agnd, probe_in;
ground agnd;
reg switch;
input enable;
logic enable;
real vinvalue;

electrical p,q;

inductor #(.l(L)) l1(p,q);
capacitor #(.c(C)) c1(q,agnd);
resistor #(.r(R)) r1(q,agnd);

initial begin
switch = 0;
end

always@(cross(V(q)-3.0-tolerance,+1)) switch=1;
always@(cross(V(q)-3.0+tolerance,-1)) switch=0;

analog begin

@(cross(V(q)-3.0-tolerance,+1));
@(cross(V(q)-3.0+tolerance,-1));

if(enable) begin
vinvalue = V(in);
if(switch==0) begin
V(p)<+ vinvalue;
end
else if(switch==1) begin
V(p)<+ 0;
end
else begin
V(p)<+ vinvalue;
end
end
else begin
vinvalue = 0;
end

V(out)<+ V(q);
V(probe_in)<+ V(p);
end

endmodule

/////////////////////////////////////////// Regulator
Code .///////////////////////////////////

Thanks in advance for your support and help.

Thanks and Regards !!!!

Cheers !!!!!

Debjit.

Dear All,

Can any one help me on this?

Early help is solicited.

Thanks and Regards !!!

Debjit.
Click to expand...
Debjit,

There are a couple of ways of solving this:

1. Ignore the red markers in HED. When you come to simulate it, the fact that
they are unbound in the hierarchy editor will not affect simulation, because
they will be bound when elaborating since they are analog primitives - so the
config view doesn't affect them.

2. Add the "sample" library to your cds.lib :

DEFINE sample $(inst_root_with:tools/dfII/bin/icfb)/tools/dfII/samples/cdslib/sample

and then in the Hierarchy Editor specify "sample" in the Library List (global
bindings).

If you do this, it will bind to the sample resistor/capacitor/inductor, but this
is purely cosmetic - it will still simulate with the analog primitives in the
simulator

I'm slightly surprised - I couldn't find any real requests for a better solution
to this (I found a customer request, but it petered out before an enhancement
request was filed).

Regards,

Andrew.
 
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