veriloga analog bus sample?

[rachelms79@hotmail.com]

Would anyone have a sample of a veriloga analog bus, eg. to define a
block to provide DAC inputs d<127:0> for a spectre simulation? I could
just define 128 input lines in the veriloga, but then in the simulation
schematic I need to wire up all 128 wires; a single bus would be easier
in the schematic.

Thanks.

 

In composer, you can define a single net to be a bus using the
following naming format "wire_name<127:0>"
you can then refer to each single bit by naming a net "wire_name<127>,
wire_name<126>.....wire_name<0>"


On Dec 13, 11:40 am, "rachelm...@hotmail.com" <rachelm...@hotmail.com>
wrote:

Would anyone have a sample of a veriloga analog bus, eg. to define a
block to provide DAC inputs d<127:0> for a spectre simulation? I could
just define 128 input lines in the veriloga, but then in the simulation
schematic I need to wire up all 128 wires; a single bus would be easier
in the schematic.

Thanks.

 

[DReynolds]

If I understand your question, here is a easy way to always get it
right:
make a schematic of the cell you want and put just pins in it
data<127:0>, clk, etc.

Then do create cellview from cellview and rather than making a symbol,
select veriloga and the software will make the module for you with all
the pins defined.

If your question is in veriloga how doI work with a digital bus, here
is a small example for a 6 bit:


parameter real vth =0.9;


integer pow2[5:0];
integer i;
integer code;








analog begin


@(initial_step) begin
for(i =0; i<6; i=i+1) pow2 =pow(2,i);
end




// decoding address
code =0;
generate i (0, 5, +1) begin
code = code + ((V(address) > vth) ? pow2 : 0);
end

The first part defines powers of 2 (1,2,4,8,etc) and the second part
tests each bit and updates the integer that represents the bus

hope this helps

David


wzhenning@gmail.com wrote:

In composer, you can define a single net to be a bus using the
following naming format "wire_name<127:0>"
you can then refer to each single bit by naming a net "wire_name<127>,
wire_name<126>.....wire_name<0>"


On Dec 13, 11:40 am, "rachelm...@hotmail.com" <rachelm...@hotmail.com
wrote:
Would anyone have a sample of a veriloga analog bus, eg. to define a
block to provide DAC inputs d<127:0> for a spectre simulation? I could
just define 128 input lines in the veriloga, but then in the simulation
schematic I need to wire up all 128 wires; a single bus would be easier
in the schematic.

Thanks.