Verilog2VHDL

[ALuPin@web.de]

Hi,

when I execute the exe-file
verilog2vhdl.exe
from http://www02.so-net.ne.jp/~morioka/v2v.htm

I see

usage: verilog2vhdl inputfile1 inputfile2 ...


If I have a file count.v
what do I have to type in ?

I've typed
verilog2vhdl count.v count.vhd OR verilog2vhdl count count
but no vhd file is created.

Rgds
André

 

[John Penton]

ALuPin@web.de wrote:

Hi,

when I execute the exe-file
verilog2vhdl.exe
from http://www02.so-net.ne.jp/~morioka/v2v.htm

I see

usage: verilog2vhdl inputfile1 inputfile2 ...


If I have a file count.v
what do I have to type in ?

I've typed
verilog2vhdl count.v count.vhd OR verilog2vhdl count count
but no vhd file is created.

Don't know the tool but I'd try:
verilog2vhdl count.v

Or more usefully:
verilog2vhdl count.v > count.vhd

--
John Penton, posting as an individual unless specifically indicated
otherwise.

 

John's 1st example is correct. To test with 'sample.v':

verilog2vhdl>verilog2vhdl.exe sample.v
Verilog2VHDL ver1.00(2004/05/06) Copyright(c) S.Morioka
(http://www02.so-net.ne
..jp/~morioka/v2v.htm)

Input file: sample.v
WARNING(0): Please modify the following component declaration
manually.
WARNING(1) in line 12: Please change the following 'std_logic_vector'
to 'std_logic', if necessary.
WARNING(2) in line 12: Please write signal width of the following
return-variable, manually.
Complete.


The result file is "sample.vhd"

(I can't believe you gave up so easily.)


ALuPin@web.de wrote:

Hi,

when I execute the exe-file
verilog2vhdl.exe
from http://www02.so-net.ne.jp/~morioka/v2v.htm

I see

usage: verilog2vhdl inputfile1 inputfile2 ...


If I have a file count.v
what do I have to type in ?

I've typed
verilog2vhdl count.v count.vhd OR verilog2vhdl count count
but no vhd file is created.

Rgds
André