verilog2001 style discussion

[Yang Luo]

1.
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
r_c <= 2'd0;
r_a <= #1 2'd0;
end
else begin
r_a <= #1 r_b;
r_c <= #1 r_b;
end
end
Is there some difference in simulation and synthsis between r_c and r_a?

2.
parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0]s_data_buff[BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< w_buff_length; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
Are the two styles both good?
reg [BIT_WIDTH-1:0]s_data_buff[BUFF_LENGTH-1:0];
I think this is an array syntax in verilog, but it cannot put on module's I/O. Do you usually use array syntax in practise?

3.
parameter DEPTH = 10;
parameter WIDTH = 8;
generate
genvar i;
for ( i = 0;i <DEPTH;i = i + 1 ) begin:data_gen
reg [WIDTH - 1:0] data;
if ( i == 0 ) begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona) data_gen.data <= { ( DEPTH ) {1'b0}};
else if ( conditionb) data_gen.data <= din;
else if ( conditionc ) data_gen.data <= data_gen[i + 1].data;
else data_gen.data <= data_gen.data;
end
end
else if ( i < DEPTH - 1 ) begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona) data_gen.data <= din;
else if ( conditionb ) data_gen.data <= data_gen[i + 1].data;
else data_gen.data <= data_gen.data;
end
end
else begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona ) data_gen.data <= din;
else data_gen.data <= data_gen.data;
end
end
end
endgenerate
Is there anybody usually use generate syntax? I kown generate syntax can use in baisc module.

 

[Mark Curry]

In article <227cd85f-3033-4b3e-a0a2-f4b841e5e49b@googlegroups.com>,
Yang Luo <youngluoyang@gmail.com> wrote:

1.
always @(posedge clk or negedge rst_n)
begin
if (!rst_n) begin
r_c <= 2'd0;
r_a <= #1 2'd0;
end
else begin
r_a <= #1 r_b;
r_c <= #1 r_b;
end
end
Is there some difference in simulation and synthsis between r_c and r_a?

Both register will have the exact same implementation in synthesis.
Synthesis ignores #delays.

2.
parameter BIT_WIDTH = 8;
parameter BUFF_LENGTH = 16;
input [BIT_WIDTH-1:0] i_data;
reg [BIT_WIDTH-1:0]s_data_buff[BUFF_LENGTH-1:0];
integer i;
2.1
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< BUFF_LENGTH; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< BUFF_LENGTH-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
2.2
wire [3:0] w_buff_length;//0--15
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
for(i=0; i< w_buff_length; i=i+1)s_data_buff <= #1 {BIT_WIDTH{1'd0}};
end
else begin
s_data_buff[0] <= #1 i_data;
for(i=0; i< w_buff_length-1;i=i+1)s_data_buff[i+1] <= #1 s_data_buff;
end
Are the two styles both good?
reg [BIT_WIDTH-1:0]s_data_buff[BUFF_LENGTH-1:0];
I think this is an array syntax in verilog, but it cannot put on module's I/O.
Do you usually use array syntax in practise?

If we're restricted to Verilog-2001, we'll use arrays, but at the ports
we'll convert to long vectors. Since, as you've noted arrays cannot be
part of a Verilog-2001 portlist. In SystemVerilog, arrays are first
class citizens, and can be used anywhere that normal vectors can (i.e.
within portlists).

3.
parameter DEPTH = 10;
parameter WIDTH = 8;
generate
genvar i;
for ( i = 0;i <DEPTH;i = i + 1 ) begin:data_gen
reg [WIDTH - 1:0] data;
if ( i == 0 ) begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona) data_gen.data <= { ( DEPTH ) {1'b0}};
else if ( conditionb) data_gen.data <= din;
else if ( conditionc ) data_gen.data <= data_gen[i + 1].data;
else data_gen.data <= data_gen.data;
end
end
else if ( i < DEPTH - 1 ) begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona) data_gen.data <= din;
else if ( conditionb ) data_gen.data <= data_gen[i + 1].data;
else data_gen.data <= data_gen.data;
end
end
else begin
always @ ( posedge clk,negedge resetn )
if ( !resetn ) begin
data <= { ( DEPTH ) {1'b0}};
end
else begin
if ( conditiona ) data_gen.data <= din;
else data_gen.data <= data_gen.data;
end
end
end
endgenerate
Is there anybody usually use generate syntax? I kown
generate syntax can use in baisc module.

Generates are powerful and useful contructs added to Verilog-2001.
They were definetly needed, and are very commonly used in
our designs.

Regards,

Mark