N
Niharika Behera
Guest
can u tell me verilog syntax of 4bit signed multiplier
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P
project Amar
Guest
On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
> can u tell me verilog syntax of 4bit signed multiplier
I can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
> can u tell me verilog syntax of 4bit signed multiplier
I can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
V
Verilog Freelancer
Guest
On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
Do you want to it?
can u tell me verilog syntax of 4bit signed multiplier
can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
V
Verilog Freelancer
Guest
On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
> can u tell me verilog syntax of 4bit signed multiplier
..
can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
> can u tell me verilog syntax of 4bit signed multiplier
..
can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
V
Verilog Freelancer
Guest
On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
> can u tell me verilog syntax of 4bit signed multiplier
..
..
i can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
> can u tell me verilog syntax of 4bit signed multiplier
..
..
i can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
R
Richard Damon
Guest
On 9/4/21 2:06 AM, Niharika Behera wrote:
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
can u tell me verilog syntax of 4bit signed multiplier
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
N
Niharika Behera
Guest
On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
this format is wrongOn 9/4/21 2:06 AM, Niharika Behera wrote:
can u tell me verilog syntax of 4bit signed multiplier
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
N
Niharika Behera
Guest
On Saturday, September 4, 2021 at 11:36:13 AM UTC+5:30, Niharika Behera wrote:
> can u tell me verilog syntax of 4bit signed multiplier...
this is my code in vivardo....
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
> can u tell me verilog syntax of 4bit signed multiplier...
this is my code in vivardo....
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
N
Niharika Behera
Guest
On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
this is my code in vivardo....On 9/4/21 2:06 AM, Niharika Behera wrote:
can u tell me verilog syntax of 4bit signed multiplier
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
On Saturday, September 4, 2021 at 11:36:13 AM UTC+5:30, Niharika Behera wrote:
can u tell me verilog syntax of 4bit signed multiplier...
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
N
Niharika Behera
Guest
On Sunday, September 5, 2021 at 1:15:34 AM UTC+5:30, verilog.f...@gmail.com wrote:
this is my code in vivado....
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
On Saturday, September 4, 2021 at 10:36:13 AM UTC+4:30, niharika...@gmail.com wrote:
can u tell me verilog syntax of 4bit signed multiplier
.
.
i can do this for you (with best way) , price : 5$ , im verilog freelancer
Do you want to it?
this is my code in vivado....
=>input [4:1] a,b;
=> output [8:1] y;
=> wire signed [7:1]a1;
=> wire signed[7:1]b1;
=>wire [16:1]mul;
assign a1[4:1]=~a|1;
assign b1[4:1]=~b|1;
assign a1[7:5]=4\'b1111;
assign b1[7:5]=4\'b1111;
assign mul=a1*b1;
assign y=mul[8:1];
endmodule
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
P
project Amar
Guest
your code is the mistake. try any way
V
Verilog Freelancer
Guest
any one can help me in this code...i am near the result but it show me error when i simmulate, it show 3 *-1=45,
but i need -3 answer.....i am dought in last 4 steps...help me...
Your code is incorrect , try other ways
T
TJ Edmister
Guest
On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera
<niharikabehera65@gmail.com> wrote:
When the result of a multiply has only the same number of bits as the
input values, there is effectively no difference between a signed and an
unsigned multiply operation. Assuming you want more than 4 bits in the
result, is there any reason why Richard Damon\'s code would not work with
\'c\' having a larger size? I have not tried it myself.
<niharikabehera65@gmail.com> wrote:
On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
On 9/4/21 2:06 AM, Niharika Behera wrote:
can u tell me verilog syntax of 4bit signed multiplier
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
this format is wrong
When the result of a multiply has only the same number of bits as the
input values, there is effectively no difference between a signed and an
unsigned multiply operation. Assuming you want more than 4 bits in the
result, is there any reason why Richard Damon\'s code would not work with
\'c\' having a larger size? I have not tried it myself.
R
Richard Damon
Guest
On 9/16/21 11:08 AM, TJ Edmister wrote:
It might be it needs to be wire signed instead of signed wire.
I don\'t do enough with signed signals to remember the syntax, so I look
it up when needed (or get the error and try the other order).
That is way I disclaimed about some details may be wrong.
If it was homework, and they couldn\'t fix that, they deserve the
problems. If it didn\'t give them enough to get started, they aren\'t
really trying to learn.
On Sun, 05 Sep 2021 01:25:16 -0400, Niharika Behera
niharikabehera65@gmail.com> wrote:
On Sunday, September 5, 2021 at 2:04:05 AM UTC+5:30, Richard Damon wrote:
On 9/4/21 2:06 AM, Niharika Behera wrote:
can u tell me verilog syntax of 4bit signed multiplier
You mean like:
signed wire [3:0] a;
signed wire [3:0] b;
signed wire [3:0] c;
assign c = a * b;
(pulled off the top of my head and may have some details wrong, you get
exactly what you paid for it).
Be prepared for a lousy implementation.
this format is wrong
When the result of a multiply has only the same number of bits as the
input values, there is effectively no difference between a signed and an
unsigned multiply operation. Assuming you want more than 4 bits in the
result, is there any reason why Richard Damon\'s code would not work with
\'c\' having a larger size? I have not tried it myself.
It might be it needs to be wire signed instead of signed wire.
I don\'t do enough with signed signals to remember the syntax, so I look
it up when needed (or get the error and try the other order).
That is way I disclaimed about some details may be wrong.
If it was homework, and they couldn\'t fix that, they deserve the
problems. If it didn\'t give them enough to get started, they aren\'t
really trying to learn.