Verilog/XST newbie question

[Cornel Arnet]

Hi there,

I'm trying to synthesize wb_dma (opencores.org) from the Xilinx
Project Navigator 6.2.03i. It's the first time that I'm using Verilog
and the Xilinx tools (I've got some experience with VHDL and Altera
tools though).

XST yields the following error:

ERROR:Xst:1468 - wb_dma_ch_pri_enc.v line 377: Unexpected event in
always block sensitivity list.

and refers to:

....
377> always @(pri_sel or pri_out0 or pri_out1 or pri_out2)
378 case(pri_sel) // synopsys parallel_case full_case
379 2'd0: pri_out = pri_out0;
380 2'd1: pri_out = pri_out1;
381 2'd2: pri_out = pri_out2;
382 endcase
....

There's something wrong with my preferences I guess...thanks.

Regards,
Cornel

 

[Marko]

You might try the following:

377> always @(*)
378 case(pri_sel) // synopsys parallel_case full_case
379 2'd0: pri_out = pri_out0;
380 2'd1: pri_out = pri_out1;
381 2'd2: pri_out = pri_out2;
382 endcase


On 17 Sep 2004 00:05:20 -0700, cornel.arnet@gmail.com (Cornel Arnet)
wrote:

Hi there,

I'm trying to synthesize wb_dma (opencores.org) from the Xilinx
Project Navigator 6.2.03i. It's the first time that I'm using Verilog
and the Xilinx tools (I've got some experience with VHDL and Altera
tools though).

XST yields the following error:

ERROR:Xst:1468 - wb_dma_ch_pri_enc.v line 377: Unexpected event in
always block sensitivity list.

and refers to:

...
377> always @(pri_sel or pri_out0 or pri_out1 or pri_out2)
378 case(pri_sel) // synopsys parallel_case full_case
379 2'd0: pri_out = pri_out0;
380 2'd1: pri_out = pri_out1;
381 2'd2: pri_out = pri_out2;
382 endcase
...

There's something wrong with my preferences I guess...thanks.

Regards,
Cornel

 

[Cornel Arnet]

Thanks for your answer. However, I assume that the downloaded code
compiles without modification. So, there must be something wrong with
the Xilinx tools preferences.

Marko <cantsay@here.com> wrote in message news:<gapnk09e3c2lrn2jb4jgiq0la9kea0tqei@4ax.com>...

You might try the following:

377> always @(*)
378 case(pri_sel) // synopsys parallel_case full_case
379 2'd0: pri_out = pri_out0;
380 2'd1: pri_out = pri_out1;
381 2'd2: pri_out = pri_out2;
382 endcase

 

[actela]

4-5 years ago, I remember the UNIX-based Synopsys/Cadence tools
were so picky about textfiles, they wouldn't even accept MS-DOS
text files. (MS-DOS terminates lines with a <CR>+<LF>.)

If you opened a MS-DOS text-file in 'vi', the end of every line
has a funny looking control-M ^M

Sort of^M
like^M
this.^M
(hehe)^M

Whenever I encounter a mysterious parsing problems (like the one
you posted), my instinct is to manually *RE-TYPE* the code in
question. In your case, manually retype the always @ line,
then delete the original line. Once in a while, I've found
embedded control-characters crash the parser, but leave no
visibly detectable error message.

Cornel Arnet wrote:

Thanks for your answer. However, I assume that the downloaded code
compiles without modification. So, there must be something wrong with
the Xilinx tools preferences.

Marko <cantsay@here.com> wrote in message news:<gapnk09e3c2lrn2jb4jgiq0la9kea0tqei@4ax.com>...

You might try the following:

377> always @(*)
378 case(pri_sel) // synopsys parallel_case full_case
379 2'd0: pri_out = pri_out0;
380 2'd1: pri_out = pri_out1;
381 2'd2: pri_out = pri_out2;
382 endcase

^^^ actually, I think most tools prefer always @* (no paranthesis.)
There was a reason for this, but I don't remember it.